ADuM4136 /FAULT and READY states

Hi,

I'm designing a motor driver using the ADuM4136.

From the datasheet Table 9, I've noticed that there are some conditions under which the READY and /FAULT pins have "UNKNOWN" states.

Can you explain this a bit more?  For instance, if power is not applied to VDD2, READY will be low, and /FAULT is UNKNOWN.

Will /FAULT maintain its last state?  Will it randomly toggle between states?

Likewise, if /FAULT is asserted during normal operation (goes low), READY has an "UNKNOWN" state listed.

If I read back LOW on both /FAULT on and READY, how can I determine if I am undervoltage/overtemperature OR have a DESAT condition?

Apologies if I am not thinking about this correctly or if it is answered elsewhere.

Thanks in advance,

Todd

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  • +1
    •  Analog Employees 
    on Mar 7, 2019 8:36 PM

    Hi Todd,

    Looking back at this truth table, I can see how it is a little confusing. I'll see if I can come up with a different representation. There are some time dependent events that make the nFAULT pin logic not purely combinatorial, which is hard to represent in the truth table. The basic things to know are:

    1) The READY pin is high if VDD2 is above the secondary side UVLO, and there is no TSD occurring. The READY pin does not depend on if there is a DESAT fault condition or not.

    2) The nFAULT pin will go low if a DESAT fault occurs, and will stay low until either of two things occur:

       a. nRESET is toggled low then high.

       b. VDD1 is toggled off then on.

    The reason nFAULT is unknown if VDD2 is unpowered is because nFAULT's condition depends on whether a fault is latched on the primary side or not. If VDD2 was powered, and a fault occurred, then for some reason VDD2 is unpowered, nFAULT would have a fault latched until nRESET or VDD1 is toggled.

    If you read back low on nFAULT and READY, it would mean

    1) a fault has occurred earlier

    AND

    2) VDD2 is below UVLO2 - AND/OR - the die temperature is too hot and the part is in TSD.

    I hope this helps. Let me know if it's not clear.

    RSchnell

Reply
  • +1
    •  Analog Employees 
    on Mar 7, 2019 8:36 PM

    Hi Todd,

    Looking back at this truth table, I can see how it is a little confusing. I'll see if I can come up with a different representation. There are some time dependent events that make the nFAULT pin logic not purely combinatorial, which is hard to represent in the truth table. The basic things to know are:

    1) The READY pin is high if VDD2 is above the secondary side UVLO, and there is no TSD occurring. The READY pin does not depend on if there is a DESAT fault condition or not.

    2) The nFAULT pin will go low if a DESAT fault occurs, and will stay low until either of two things occur:

       a. nRESET is toggled low then high.

       b. VDD1 is toggled off then on.

    The reason nFAULT is unknown if VDD2 is unpowered is because nFAULT's condition depends on whether a fault is latched on the primary side or not. If VDD2 was powered, and a fault occurred, then for some reason VDD2 is unpowered, nFAULT would have a fault latched until nRESET or VDD1 is toggled.

    If you read back low on nFAULT and READY, it would mean

    1) a fault has occurred earlier

    AND

    2) VDD2 is below UVLO2 - AND/OR - the die temperature is too hot and the part is in TSD.

    I hope this helps. Let me know if it's not clear.

    RSchnell

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