I have some questions about ADuM12xN.
Both VDD1 and VDD2 have UVLO. Right?
If input side VDD goes lower than UVLO level, the output will be default output.
Example if the device is N0, the output will be Low. Right?
What will happen if the output side VDD goes lower than UVLO.
The output will be HiZ?
I think ADuM12xN have POR(Power on reset) level.
Can you tell the value to us?
And I think if the input side VDD is lower than POR, the output will be default value.
But what will happen if the output side VDD be lower than POR?
the answer to the first 3 question is yes.
The POR circuit does not monitor VDD directly. it is controlled by UVLO circuit after adding some filter time. so POR level is almost equal to UVLO level.
Thank you for your reply.