ADUM315x / ADUM3151 / ADUM3152 / ADUM3153 speedgrade question

Hello together,

I have a question concerning ADUM315x parts and speedgrade A and B:

In datasheet you can find the followoing information:

Later in technical description of the datasheet there are more detailed information;

So my question why is speedgrade A specified for 1MHz only? If glitch filter is the only difference between those parts maximum speed should be higher and not differ so much to speedgrade B. We have tested to clock ADUM3151

A with more then 1MHz (up to 5MHz) without having a problem in communication. In that case propagation delay is still smaller then clock frequency.

Anyhow we doubt to do that because when refering to datasheet we would operate the part beyond specification.

Could you provide some more information concering that issue? When using information provided in should be a problem to increase data rate a speed grade A type.

Thanks in advance

Christian



formating
[edited by: intec at 10:41 AM (GMT 0) on 6 Feb 2019]
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  • 0
    •  Analog Employees 
    on Feb 6, 2019 8:26 PM over 1 year ago

    Hi Cristian, 

    The A-grade and B-grade are actually different. The SPI bus channels in the A-grade have a ~10ns glitch filter. In the B-grade, the glitch filter is removed from the clock, MOSI and MISO channels (the MSS channel has a glitch filter in both grades).

    There are two specifications that can limit the SPI clock frequency. I'll talk about just "standard" isolated SPI here, or where data is clocked out on the first clock edge, clocked in on the next clock edge, and the isolator is simply inserted into the bus... The first is the propagation delay. Half the clock period must be greater than 2x prop delay maximum. The second is the maximum data rate or min pulse width. Its the max data rate spec limiting the SPI clock frequency through the ADuM3151 A-grade. 

    Its not surprising that it can be operated at 5MHz. Its not a brick wall, but the PWD could be going out of specified ranges, and operation over the full voltage and temp ranges can't be guaranteed. So if the application needs to run at 5MHz, and it is not a very noisy environment, I recommend moving to the B-grade.  

    Regards,

    Jason

Reply
  • 0
    •  Analog Employees 
    on Feb 6, 2019 8:26 PM over 1 year ago

    Hi Cristian, 

    The A-grade and B-grade are actually different. The SPI bus channels in the A-grade have a ~10ns glitch filter. In the B-grade, the glitch filter is removed from the clock, MOSI and MISO channels (the MSS channel has a glitch filter in both grades).

    There are two specifications that can limit the SPI clock frequency. I'll talk about just "standard" isolated SPI here, or where data is clocked out on the first clock edge, clocked in on the next clock edge, and the isolator is simply inserted into the bus... The first is the propagation delay. Half the clock period must be greater than 2x prop delay maximum. The second is the maximum data rate or min pulse width. Its the max data rate spec limiting the SPI clock frequency through the ADuM3151 A-grade. 

    Its not surprising that it can be operated at 5MHz. Its not a brick wall, but the PWD could be going out of specified ranges, and operation over the full voltage and temp ranges can't be guaranteed. So if the application needs to run at 5MHz, and it is not a very noisy environment, I recommend moving to the B-grade.  

    Regards,

    Jason

Children
  • Hi Jason,

    thanks for the quick answer and detailed information.

    That means if we can guarantee min. PWD limit of 100ns and we are sure that temperature will not vary so much operating speedgrade A device will work in limits up to 5MHz without restrictions.

    For our application is sufficient and having glitch filter in data signals is a big advantage in application.

    Regards

    Christian

  • 0
    •  Analog Employees 
    on Feb 7, 2019 8:50 PM over 1 year ago in reply to intec

    Hi Christian, 

    You will be going outside of the datasheet because the SPIMCLK spec maximum is 1MHz. As you pointed out the minimum supported pulse width is 100ns, which does work out to be 5MHz... I don't have a design reason the A-grade could not do this though. 

    Could you reach out to your local ADI contact on this application? We can work out how to support this application at 5MHz with the A-grade.

    Thanks and Regards,

    Jason