M-LVDS Design - Link Layer and recommended example microcontroller

I am trying to evaluate options for a back-plane interface ( order of 20-50Mbps or higher) with cost being a major driving factor. I seem to have narrowed down to either M-LVDS or RS485 (I've seen xcvrs in the 25Mbps range, which may be also be OK).  What I am looking for is:

1. A good reference design/application note or any data that shows this back plane design implementation?

2. Given that the speeds are 50Mbps, what would be the recommended link layer ? Any recommendations on the TI micro controllers that can be interfaced to these bus xcvrs? Are there any micro controllers supporting high speed serial interfaces (considering UARTs on existing uC may not be suitable)



  • Hi R,

    Although back plane design isn't specifically covered in detail, we do have an application note on LVDS and M-LVDS:


    Additionally high-speed (50 Mbps) Rs-485 is discussed in the context of motor control encoders in the following application note:


    Regarding the limitations of UARTs, ADI do have processors such as ADSP-CM408F with a high-speed serial interface (SPORT) that could be used, or an alternative would be to use SPI over RS-485 or M-LVDS, if the processor supports higher SPI clock rates. FPGAs are another alternative for high-speed I/O.

    M-LVDS transceivers are operated in a similar way to RS-485 transceivers, and even have the same pin-out, so you could possibly test both with the same PCB if the software is configured to handle the different "failsafe" default logic "1" or "0" for the idle bus. RS-485 will be more robust and allow longer cables, while M-LVDS is still designed to drive longer PCB traces and even short cable interconnects, and is lower power, but robustness is still limited by the -1V to 3.4V common mode range.