I am trying to use two ADG3304-EP connected with two AD5141W, on the same SPI bus going to an FPGA.
My concern is due to the fowling sentences from the ADG3304 datasheet -
When the application requires level translation between a micro - processor and multiple peripheral devices, the ADG3304 I/O pins can be three -stated by setting EN = 0. This feature allows the ADG3304 to share the data buses with other devices without causing contention issues.
I prefer not to use the EN pin but rather have it constantly tied up. I prefer to interface the two ADG3304 directly to the SPI bus and use the CS signals to tell the digital pots when to "talk".
Do you see any issues with this set-up?
Also, do you think that there some specific interface issues i may encounter?