ADM3260 performance in a two layer PCB

Hi Javier, 

It may be possible with very careful layout to meet Class A on a two layer. Best for emissions would be to use a 4-layer board and use the inner layers to create stitching capacitance. 

There may be an easier way to meet emissions targets on two layer board. The new ADuM5028 is designed to meet Class B emissions on a 2-layer board. Then use the ADuM1250 I2C isolator for the SDA and SCL lines.

Regards,

Jason

Hello Jason, thanks for your reply.

Where may I find guidelines for the layout of the ADM3260 on 2 layer PCB?

The application I´m working is a PH meter. I´m worried that the emissions could mess up the measurement ratter than not meeting Class A.

Thanks again,

Javier.

Hi Javier, 

There isn't documentation specific to the ADM3260 layout on a 2-layer board. There will have to be some experimentation here. AN-0971 provides general information. 

There are two major things to consider. The first is stopping the noise from the isoPower dc/dc converter from making it to the secondary side. That's going to require the use of ferrites in series with the VISO and GNDISO pins before going to the pcb's isolated power and gnd planes.

The second consideration is providing a high frequency return path to the primary side. Its most effective to form a capacitor with the inner layers of the pcb. A  2-layer pcb doesn't have inner metal layers, so safety caps placed closely to the ADM3260 would have to be used instead.  

Still, since you are restricted to a two layer board and sensitive to noise, it may be easiest to use the latest generation of isoPower devices for power (ex. ADuM5028) or an I2C uModule like the LTM2886.

Regards,

Jason

Hello Jason, thanks for your quick reply.

Regarding the ferrites 2k @100Mhz would it be OK?

Should I keep one of the layers for GNDISO only and the other one for VISO and signal traces? Or should I have a GNDISO plane on both layers and stich them together

I don´t undertstand the second consideration (high frequency return path to the primary side), using safety caps.

The devices I have to power consume very little current (5 to 10 [ma] max for powering an ADC and OPAMP), the generated noise would likely be little as well?

Thanks again,

Javier.

Hello Jason, thanks for your quick reply.

Regarding the ferrites 2k @100Mhz would it be OK?

Should I keep one of the layers for GNDISO only and the other one for VISO and signal traces? Or should I have a GNDISO plane on both layers and stich them together

I don´t undertstand the second consideration (high frequency return path to the primary side), using safety caps.

The devices I have to power consume very little current (5 to 10 [ma] max for powering an ADC and OPAMP), the generated noise would likely be little as well?

Thanks again,

Javier.