I need to level translate an I2C bus from a uP master at 3.3V down to a 1.2V slave for an FPGA.
Thus the uP is master and drives SCL and SDA into the SCLOUT and SDAOUT pins. Does this actually work that the SCL drives into SCLOUT and out of SCLIN?
It does appear that both the data and clock are bidirectional and can drive either direction.
Does this sound correct?