Currently, I have following questions . Can you confirm it?
1) When ADN4668 is power-off, how is phy configured LVDS Rx side in ADN4668? For example, is that a Hi-Z?
2) If 1) is not Hi-Z, when there is DC at LVDS Rx side, we want to know whether ADV4668 don’t leak a current from any pin.
When ADN4668 is power-off, the LVDS receiver will be high impedance. As a result any voltage applied to the receiver pins will result in very little current flow (either from LVDS to GND, or through the unpowered supply on Vcc depending on its impedance in the power-off state).
No external circuit or pull-down is required for the power-off condition.