How can you explain following behavior please:
Status primary side:
VI- tied to VSS1
VDD1 +3,3V with respect to VSS1 (always guaranteed not to exceed chip limits, protected with TVS)
VI+ valid PWM signal (+3,3V or 0V with respect to VSS1)
Status secondary side:
GND2 tied to VSS2
VDD2 +15V with respect to VSS2 (always guaranteed not to exceed chip limits, protected with TVS)
DESAT low (tied to VSS2)
VOUT low, not changing, not driving the FET
Chip temperature low (below 30 °C).
The chip enters this faulty behavior randomly, without clear cause, after 5-20 sec of operation.
Only chip cold reset, i.e. turning off VDD1 and VDD2 and turning them again after ca 1 sec. helps. The chip resumes normal operation then.
Observed PCB layout precautions in the datasheet.
When chip temperature is higher (assuming >40 °C) then entering this faulty state is much less frequent.
After replacing one chip with another the behavior is roughly the same.