ADUM4136 weird behavior

How can you explain following behavior please:

Status primary side:

VI- tied to VSS1

VDD1 +3,3V with respect to VSS1 (always guaranteed not to exceed chip limits, protected with TVS)

VI+ valid PWM signal (+3,3V or 0V with respect to VSS1)

/RESET low

/FAULT high

READY high

Status secondary side:

GND2 tied to  VSS2

VDD2 +15V with respect to VSS2 (always guaranteed not to exceed chip limits, protected with TVS)

DESAT low (tied to VSS2)

VOUT low, not changing, not driving the FET

Chip temperature low (below 30 °C).

The chip enters this faulty behavior randomly, without clear cause, after 5-20 sec of operation.

Only chip cold reset, i.e. turning off VDD1 and VDD2 and turning them again after ca 1 sec. helps. The chip resumes normal operation then.

Observed PCB layout precautions in the datasheet.

When chip temperature is higher (assuming >40 °C) then entering this faulty state is much less frequent.

After replacing one chip with another the behavior is roughly the same.

  • 0
    •  Analog Employees 
    on Oct 24, 2018 6:35 PM

    Hello,

    Thanks for the excellent detail in your test configuration. I will attempt to recreate these conditions. I have a few questions:

    1) What datecode are the parts? This is the four digit number following the # symbol on the IC top marking

    2) When /RESET is "low", is it tied to VSS1, meaning there is no output on the Vout pin?

    Thanks,

    RSchnell

  • Hi!

    1)#1617, all the same

    2)I am sorry, /RESET high, checked wrong pin before. Always tied actively to VDD1 except for reset pulse which I have to issue by hand. Other pin states as described above.

    I suspect some problem with master logic primary/secondary inside the chip.

  • 0
    •  Analog Employees 
    on Oct 24, 2018 9:16 PM in reply to tk_

    Hello,

    I've recreated the conditions on my bench. I have limited parts from the #1617 datecode available to me, but managed to run one on an ADuM4136 evaluation board.

    Here are my current test conditions:

    VDD1 to VSS1 = 3.3 V

    VI+=500 kHz 50% duty square wave 0 to 3.3 V. High-Z output setting on signal generator

    VI- = shorted to VSS1

    VDD2 to GND2/VSS2 = 15 V

    No load on output (except for oscilloscope probe)

    Room temperature ambient

    nReset shorted to VDD1

    nFault pulled up to VDD1 with 10 kΩ

    READY pulled up to VDD1 with 10kΩ

    C6 on eval board shorted (to short DESAT pin to GND2)

    So far, the ADuM4136 has been running for several minutes without a fault registering. I'll leave it running overnight, and then vary the operating conditions. I'm also attaching a screenshot of the part operating. Ch. 1 = VDD1. Ch. 2 = Vout. Ch. 3 = VI+. Ch. 4 = nFault

    I'll keep you posted with how the testing goes. There is a bit of noise in my measurements due to the long probe ground leads I'm using. There is some overshoot/undershoot on Vout since it is not damped with a load.

    RSchnell

  • Hello RSchnell

    thank you for such an effort. I suspect that increased noise/disturbance is cause in our circuit. My other tests report that the fault comes on high duty cycles and when high currents flow through the attached mosfets (ca 5A and more), which of course causes substantial ringing.

    We attach 2 power mosfets STY139N65M5 in antiseries configuration (bipolar switch) with both gates driven with single ADUM4136 chip. It is high side switching. DC/DC is MEJ1S0515SC.Now we have Rg (gate resistor) 1 Ohm for both mosfets. When Rg is 10 Ohm the faults nearly don't occur. I expect even bigger Rg would solve it. But we cannot use big Rg because of switching efficiency.

    Regardless of the ringing/disturbance I think the chip should not have such faulty behavior even under very harsh conditions.

  • 0
    •  Analog Employees 
    on Oct 25, 2018 9:15 PM in reply to tk_

    Yes, I agree that a gate driver must be robust, even in noisy environments. This issue is very important to us and we will continue working on it to find a solution. I appreciate all the information you've supplied.

    We have performed EFT testing on the gate driver during development, and did not see false DESAT events when noise was injected onto the parts. The EFT test injects burst of noise in pulses, and in our testing we injected it into VDD2. It is possible that the test does not mimic the same noise that your application is seeing. I'm hoping to get a little more information about the noise your setup is experiencing.

    To double check, when Vout is low, the following conditions are present:

    /RESET high

    /FAULT high   <---- is this correct?

    READY high

    If /FAULT is high, the primary side does not see a false DESAT. If READY is high, it means the secondary side is not in UVLO, and is able to send a heartbeat to the primary side, suggesting it is no latched-up.

    1) Do you have any waveform captures of the power rails of the ADuM4136?

    2) What decoupling is on VDD2 to GND2 and VSS2 to GND2 (in the bipolar case) is being used? I usually put 0.1 µF + 10 µF on the secondary side power rails.

    3) Is the DESAT pin tied to GND2 through a resistor, or directly shorted? If it is tied with a resistor, what is the value? This should be as low as possible.

    4) When the nFault line goes low, and you have to cold reset the part, have you tried toggling the nReset pin? If so, does the part clear the fault when the nReset pin is toggled? Have you tried just unpowering VDD2 and repowering it?

    5) After the situation, does the quiescent current of the ADuM4136 go dramatically up? I'm asking in case there is some kind of latch-up condition. If a cold reset is the only way to reset the part (see question 4) it would suggest a latch-up is occurring, not just a standard fault (either real or false).

    6) Is there any large RF source in the testing area? It is curious to us that an ADuM4136 not attached to a power stage could exhibit this false DESAT. The reporting transmission uses the same type of  internal transmission coil as the forward path, so if noise is coupling into the internal transmission, we would expect to see the output go falsely high sometimes. This would take a large, sustained RF (100's of MHz) signal nearby.

    If DESAT is not needed, may I suggest looking at the ADuM4120 or ADuM4121? They are able to be operated in bipolar mode with use of some external circuitry:

    https://www.analog.com/en/analog-dialogue/raqs/raq-issue-158.html

    They have half the drive strength of the ADuM4135, but they are still very strong drivers. Our 2 A rating on the ADuM4120 and ADuM4121 is not the short circuit peak current, but the intended application typical value. In reality, they can operate with a 1 Ω external series resistor in most cases, depending on operating frequency, ambient temperature, and load, of course.

    Thanks again for all your work in this investigation. I hope we can help you with your application.

    RSchnell