If we see an error in the pixel, we basically duplicate the previous good pixel so in effect what the customer will see is that
the pixel is delayed by 1 when the pixel is bad/gone. But in reality a bad…
The answer is yes. but please follow the setup sequence. Otherwise, the control channel will be not stable.
set-up sequence.
// disable the forward control channel receiver
1. 90, 0x04,0x00, …
The coupling capacitors at the inputs/outputs should be 220nF for GMSL using the normal reverse channel and 47nF for parts using High Immunity Mode, ideally with the REV_FAST bit set to '1' which increases…
MAX9288 does not have register setting to turn off the output. The users can power down the part by setting /PWDN low (clock is LP-00 state), then power up the part again by setting /PWDN high (the clock…
Generally, this means that MIPI output is correct, need to check the receiver’s MIPI speed setup first. Second, there is setting sequence requirement from the deserializer MIPI output enable to MIPI receiver…
We do not recommend using any device in between the GMSL link. The GMSL link between the SER and DES already has an AC coupled capacitor to isolate the LVDS channel from DC bias levels in the first place…
Yes, the MAX96705 is compatible with the MAX9288. However, there are some considerations for configuring these parts to work together. The MAX96705 and MAX9288 support different maximum serial bit rates…
The MAX9288/90 are compliant to the MIPI CSI-2 V1.1 and D-PHY V1.1 specification up to maximum lane rate of 1Gbps.
In pactice this can be summarised as:
Lane speed Min 80Mbps, max 1Gbps
Continuous…