Question:
What is the typical delay time between the input change and DI data reading, when connecting two MAX22190 in daisy chain mode?
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Answer:
Let’s assume customer is using this part in bypass filtering mode (no programmable digital filtering):
Input filter delay, 2us typical. This is the delay between input signal and internal comparator output.
Sampling delay, 1us typical. This comes from the samples rate of 1MHz as shown in the EC table.
LATCH\ or CS\ delay, 50ns. This is the internal delay between the LATCH\ or CS\ pin change to the data locked in the DI register.
SPI data reading delay. This delay depends on the SPI master’s timing, and is not controlled by the MAX22190. Typically, we need to consider the delay between the CS\ going low to first SCLK (tCLK_SU), SCLK speed and number of bits, the delay between the last SCLK to CS\ going high (tCSBH), CS\ high pulse width (tCSPW), and repeat for the second command. We know that the SPI clock is 10MHz. So the total SPI delay can be calculated as:
SPI delay = tCLK_SU + 32*100ns + tCSBH + tCSPW + tCLK_SU + 32*100us + tCSBH
If we are using the minimum value of tCLK_SU, tCSBH, and tCSPW as defined in the EC table, the minimum SPI delay can be 80ns + 3200ns + 40ns + 20ns + 80ns +3200ns + 40ns = 6.66us
So the minimum total delay between input change and data reading in daisy chain of 2 devices can be 9.71us.
Please note we get this number in the case that SPI timing specs are all minimum as shown in the EC table.
In reality, these delays (tCLK_SU, tCSBH, and tCSPW ) can be much larger, which contribute to the total delay between the input change and data reading.