There could be multiple reasons for OUT_ switches on MAX14917 turning off automatically despite the IC being enabled.
The fastest way to debug this would be by inspecting the error bits on SDO, i.e. response from MAX14917.
If CRC is enabled, on sending the following data on SDI (ON8, ON7,ON5,ON4,ON3,ON2,ON1, 0, 0, 0, CRC4,CRC3,CRC2,CRC1, CRC0), the users should receive fault bits (F8-F1) followed by cmer, verr, therr and CRC (if enabled) on SDO by MAX14917.
If any of the error bits (i.e. CMERR, VERR, THERR) are set, outputs will not switch or turn off automatically.
- The CMERR bit is set when either an SPI or SYNCH watchdog event has occurred. The SPI watchdog timer monitors clock activity on the CLK and inputs. At least one valid SPI cycle must be detected in the watchdog-timeout period. This means that the CLK input must have a multiple of 8 clock-cycles during a low period. To rule out this error, users can try disabling SPI watchdog by setting SPIWD low. The SYNCH pin watchdog checks if SYNCH is stuck low. At least a 1µs SYNCH pin high level must be present in the watchdog-timeout period. Driving the SYNCH pin high if SYNCH is not used ensures that the SYNCH watchdog is disabled. To rule out this error, users can disable the SYNCH watchdog if they are driving SYNCH pin high forever by setting SYNCHWD low.
Watchdog timers (SPIWD and/or SYNCHWD) monitor SPI and/or SYNCH activity, and automatically turn the OUT_ pins off in case of missing SPI/SYNCH activity when enabled.
- The VERR bit is set if either of the VDD, VA, or internal voltages is below their nominal operational thresholds.
- The THERR bit is set when a chip thermal shutdown event has occurred.
Users can also pull up FAULT_N and COMERR_N pin to ensure it is not a CRC error or an underload/overload fault condition. COMERR pin is set low when CRC error is detected. FAULT pin is set low due to underload or overload conditions.
In any of the cases. output switches will not change or will automatically be turned off despite the MAX14917 IC being enabled.