Regarding the ADI Ethernet transceiver (PHY) ADIN1200 (model number: ADIN1200BCP32Z),
I would like to make the following inquiry regarding the behavior of the clock output when the PHY detects a link-down.
The PHY speed setting is set to 100FD with auto-negotiation disabled.
The measured input voltage of PHY_CFG0 at startup is 2.8V.
PHY_CFG1 is 2.3V, and measurements have confirmed that both are within the MODE3 range.
When operating with the above settings, we have confirmed that the TX_CLK output drops from 25MHz to 2.5MHz within 10us of detecting a link-down.
・Question 1: Please tell me why the above behavior occurs.
I have looked at the data sheet, but I still don't understand the cause of the above behavior, so I would appreciate it if you could explain.
・Question 2: Please tell me what settings I need to make so that the 25MHz clock output continues even when the link is down.