Latency - 10BASET1L, ADIN2111

Hi inagore 

Thanks for pointing that out.

The above transmit latency of 7.2us is correct for RevA generic SPI protocol. The 4 byte RevA TxHeader, followed by the two byte frame header and the 2 TX_THRESH bytes have to be transferred over the SPI before the frame transmission can start in the PHY, i.e. a total of 8 bytes, which would take 8 * 8 * 62.5 ns = 4,000 ns = 4 us + PHY Tx latency = 3.2uS 

Total Tx Latency = 4us + 3.2us = 7.2us

For OA SPI protocol, the latency measured from the first bit following the (OA-SPI) TX header and TX_EN assertion is between 1.4us and 1.8us. Including the 4 bytes (2 us) Rev B Tx header, this adds up to 3.4uS and 3.8us which brings the total Tx latency to around 6.8us.

The 2 byte of TX_THRESH accounts for 1us. The variable part (0.4us to 0.8us) is due to the transfer between 62.5 ns SPI clock domain and the 400 ns MII TX_CLK clock domain. It is between about 1 and 2 MII clock periods and is probably due to some TX FIFO.

The SPI clock is a 16 MHz clock and the MII clock is a 2.5 MHz clock, so even though they are synchronous they do not have a fixed phase relationship.

Hope this helps.

Regards,

Shazia