Clarification on Tx/Rx Latency Specifications for ADIN1110

Hello,

I’ve reviewed the Q&A postings on the ADIN1100 latency and time synchronization accuracy (links below) and found them helpful. However, I need additional details specific to the ADIN1110, particularly regarding jitter or short‐term variations in access time. We rely on the ADIN1110 not just for data transmission but also as a heartbeat link in a functional‐safety application, so deterministic behavior is critical.

Could you please clarify:

1. Jitter/Short‐Term Variations

   • Are there published specs for how much variation (min/max or typical) we can expect in the ADIN1110’s Tx/Rx latency (including MAC + PHY) under normal operating conditions?
   • What are the main contributors to this jitter (e.g., internal buffering, clock drift, temperature/voltage changes)?

2. Guaranteed Worst‐Case Latency

   • Beyond the typical numbers, do you provide guaranteed max latency specifications?
   • In particular, for short frames (e.g., 64 bytes) at 10 Mbps, can you share a worst‐case access time figure factoring in internal overhead?

3. Calibration or Configuration Options

   • Are there any registers or configuration steps we can use to minimize or calibrate out latency jitter in the ADIN1110?

4. Functional‐Safety Considerations

   • Has the ADIN1110’s latency performance been validated or characterized for safety‐critical applications?
   • Do you have any recommended design practices to ensure the link remains deterministic over the full temperature/voltage range?

Links Reviewed:

• ADIN1100 Latency Q&A
• Time Synchronization Accuracy on ADIN1100

Thank you in advance for any additional information you can provide. Understanding the jitter and worst‐case latency is key for our functional‐safety design.

Best regards,
WB