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EVCU_DEVC || ETHERNET PHY INTERFACE SCH REVIEW || ADIN1200|| ANALOG

Category: Hardware
Product Number: ADIN1200
We are working on the new EV Charger design and as per the customer requirement we are going to use Ethernet Phy chip (ADIN1200CCP32Z) in our design for factory programming purposes.
Please help to review the schematic section from your end and let me know if any update is required from our side.
I am attaching one sheet of ethernet signal pin mapping Vs processor pin mapping and Schematic section and Block Diagram.
  • MAC is IMX.93
  • RMII is the interface
S.NO PIN.NO ADIN1200CCP32Z PIN TYPE POWER DOMAIN IMX93 (RMII) PIN TYPE PIN VOLTAGE IN PROCESSOR
1 7 XTAL_O O/P AVDD_3P3 NC  -  -
2 8 REF_CLK I/P AVDD_3P3 ENET1_TD2 O/P 3V3
3 17 INT_N/CRS O/P VDDIO ENET1_Nint I/P 3V3
4 18 MDC I/P VDDIO ENET1_MDC O/P 3V3
5 19 MDIO I/O VDDIO ENET1_MDIO O/P 3V3
6 6 RESET_N I/P AVDD_3P3 ENET1_nRST O/P 3V3
7 1 TXD_0 I/P VDDIO ENET1_TD0 O/P 3V3
8 2 TXD_1 I/P VDDIO ENET1_TD1 O/P 3V3
9 3 TXD_2 I/P VDDIO ENET1_TD2 O/P 3V3
10 4 TXD_3 I/P VDDIO NC  -  -
11 23 RXD_3/PHYAD_3 O/P VDDIO NC  -  -
12 24 RXD_2/PHYAD_2 O/P VDDIO NC  -  -
13 26 RXD_1/PHYAD_1 O/P VDDIO ENET1_RD1 I/P 3V3
14 27 RXD_0/PHYAD_0 O/P VDDIO ENET1_RD0 I/P 3V3
15 28 RXC/RX_CLK/MACIF_SEL0 O/P VDDIO NC  -  -
16 29 RX_CTL/RX_DV/CRS_DV/ MACIF_SEL1 O/P VDDIO ENET1_RX_CTL I/P 3V3
17 31 TXC/TX_CLK I/P VDDIO NC  -  -
18 30 TX_CTL/TX_EN I/P VDDIO ENET1_TX_CTL O/P 3V3
19 21 GP_CLK/RX_ER/MDIX_MODE O/P VDDIO ENET1_RXC I/P 3V3

  • Hi Chanchal,

    The schematic looks correct overall. The PHYAD and MAC_SEL pins have internal pull-down resistors, so the optional pull-down resistors may not be required. 

    The block diagram shows a TXD_2 connection while the schematic shows that the same pin is disconnected. TXD_2 is not used in RMII so the schematic is correct. 

    Also, note that RMII needs a 50MHz clock.

    I am not familiar with IMX93 so I can't comment on whether the ADIN1200 signals are connected to the correct pin of IMX93.

    regards,

    Mark

  • Thanks mark for the update,
    Yes in the block diagram it missed, but it schematic is NC as we are on the RMII interface.
    And IMX93. MAC. ref clock is 50 MHz.