ADIN1200 No Linking/Autonegotiation timing problem

Hi,

 The schematic that you have provided looks to match with the Reference Design. Have you performed the required ADIN1200 Register writes to enable the ADIN1200 to operate as a Media Converter? Please see below for a description of the register writes needed to configure the ADIN1200 for Media Converter applications.

• RMII RX/TX interfaces are not functionally compatible (not supported by the RMII specification), so by default aren’t intended to be connected back to back directly. However, there is a bit field provided in the ADIN1300 which allows configuration of back to back mode with the RMII interface. If connecting the ADIN1300 to another ADIN1300 (or ADIN1200), set GE_RMII_CRS_EN to 0 in the GE_RMII_CFG register. This will disable CRS encoding on CRS_DV, so it can be connected to TX_EN.
• In 10BASE-T mode and with any of the MAC interfaces, the 10BASE-T receiver can remove several preamble bits, so the RX data would have <7 preamble bytes. This could cause problems for the remote end receiving the frame. To avoid any issues, enable the 10BASE-T RX preamble re-generation by setting the GE_B10_REGEN_PRE register (address 0xFF38) to 0x1.

The register redback that you have provided, are they from your board, or are they from the working reference design board?

Is the link partner you are connecting too also Advertising 10M speeds?

Could you provide register readbacks from the ADIN1200 for Registers 0x00 to 0x1F from your design?

Best Regards,

Mark

Hi Mark,

thanks for your reply.

MarkBolger said:

• RMII RX/TX interfaces are not functionally compatible (not supported by the RMII specification), so by default aren’t intended to be connected back to back directly. However, there is a bit field provided in the ADIN1300 which allows configuration of back to back mode with the RMII interface. If connecting the ADIN1300 to another ADIN1300 (or ADIN1200), set GE_RMII_CRS_EN to 0 in the GE_RMII_CFG register. This will disable CRS encoding on CRS_DV, so it can be connected to TX_EN.
• In 10BASE-T mode and with any of the MAC interfaces, the 10BASE-T receiver can remove several preamble bits, so the RX data would have <7 preamble bytes. This could cause problems for the remote end receiving the frame. To avoid any issues, enable the 10BASE-T RX preamble re-generation by setting the GE_B10_REGEN_PRE register (address 0xFF38) to 0x1.

These Settings are set, but the problem is still there.

MarkBolger said:

The register redback that you have provided, are they from your board, or are they from the working reference design board?

These are the same for both boards.

MarkBolger said:

Is the link partner you are connecting too also Advertising 10M speeds?

I think so. 100M definetly. The Dev Board is working with the same partner.

Here the register readback:

07:17:58.346 -> Phy:8, Reg:0, Value:1100
07:18:02.133 -> Phy:8, Reg:1, Value:7949
07:18:06.303 -> Phy:8, Reg:2, Value:283
07:18:10.166 -> Phy:8, Reg:3, Value:bc20
07:18:13.630 -> Phy:8, Reg:4, Value:45
07:18:16.860 -> Phy:8, Reg:5, Value:0
07:18:19.733 -> Phy:8, Reg:6, Value:64
07:18:23.161 -> Phy:8, Reg:7, Value:2001
07:18:26.707 -> Phy:8, Reg:8, Value:0
07:18:30.058 -> Phy:8, Reg:9, Value:0
07:18:35.507 -> Phy:8, Reg:A, Value:0
07:18:39.366 -> Phy:8, Reg:B, Value:0
07:18:49.860 -> Phy:8, Reg:C, Value:0
07:18:55.665 -> Phy:8, Reg:D, Value:0
07:18:59.626 -> Phy:8, Reg:E, Value:0
07:19:03.195 -> Phy:8, Reg:F, Value:0
07:19:10.167 -> Phy:8, Reg:10, Value:0
07:19:16.211 -> Phy:8, Reg:11, Value:0
07:19:20.408 -> Phy:8, Reg:12, Value:402
07:19:23.792 -> Phy:8, Reg:13, Value:1051
07:19:29.394 -> Phy:8, Reg:14, Value:0
07:19:32.598 -> Phy:8, Reg:15, Value:1
07:19:36.057 -> Phy:8, Reg:16, Value:400
07:19:39.355 -> Phy:8, Reg:17, Value:3048
07:19:42.740 -> Phy:8, Reg:18, Value:1
07:19:46.062 -> Phy:8, Reg:19, Value:100
07:19:49.701 -> Phy:8, Reg:1A, Value:304
07:19:54.154 -> Phy:8, Reg:1B, Value:401
07:19:57.203 -> Phy:8, Reg:1C, Value:2109
07:20:01.014 -> Phy:8, Reg:1D, Value:1855
07:20:04.901 -> Phy:8, Reg:1E, Value:0
07:20:09.757 -> Phy:8, Reg:1F, Value:83fc

Best regards,

Simon

Found the Problem in the TXEN Pin.
Interesting is, that Auto Negotiation won't work with a false TXEN Signal. Linking without AN was possible.

--CLOSED--

Hi Simon,

Thank you for the update.

Best Regards,

Mark