Strapping for two level pins

The two Pins for selection of the MAC-Interface used and the four PhHY address pins, feature a internal pull-down resistor of  45kOhm.

The levels for 2 Level Pins are like MODE_1(<0,1 * VDDIO) and MODE_4 (>0,9 * VDDIO)

Therefore if the internal pull-down is taken into account the strapping should be done with at least with an 3.9kOhm pull-up resistor.
The datasheet actually suggest a even higher level of 2,5kOhm, although it is only suggested in regards to a FPGAs, which could act as a external pulls on the pins, not the internal pull-down of the PHY. 

When following the EVAL-ADIN1300FMCZ as an implementation example a 10kOhm resistor is used.

Whats the right way of pulling on these pins, maybe the datasheet need some clarification regarding this topic.
The other option is that the EVAL-Board is wrong? If so I suggest an update to its documentation.