I am measuring power consumption on the AVDD_H, AVDD_L, and VDDIO rails for the EVAL-ADIN2111, and am seeing higher-than-expected consumption. I'd like to understand why this is the case, and get help lowering the power consumption.
I have the ADIN2111 connected to a STM32L496 nucleo board, with the processor onboard the ADIN2111 held in reset. With all 3 buses (AVDD_H, AVDD_L, and VDDIO) powered from 3V3, and the system idling (both PHY activated, and connected in loopback from link 1 to link 2, but not sending or receiving any data), I am seeing a total of 232mW -- 120mW on AVDD_H, 100mW on AVDD_L, and 12mW on VDDIO. This total of 232mW somewhat exceeds the spec given in the datasheet for single-supply, 2.4Vp-p operation at "100% data throughput, full activity" -- the datasheet lists a max power consumption in that state of 215mW. Moreover, given that no data is being sent or received, I would expect a power consumption significantly lower than the spec of 215mW.
1. What is the expected power consumption for an ADIN2111 when the links are active, but not sending or receiving data?
2. Why is my consumption higher than levels described in the datasheet, and what can I do to lower it?
Attached photos: hardware setup. Yellow arrow to show where I am probing power (joulescope inputs replace jumper P14).