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ADIN1110 - Content of Frame sent over SPI



		

			

									
					    Katharsis
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 13, 2022 
				
			
			
		
    

				
		
    
		    		    
		    
		    		            		        
    Category: Software
    
    		        		            		    
    Product Number:  ADIN1110 
    
    		        		    		    	
			
    Hello community,
    

    I have some trouble to understand the content for the data sent over SPI to the ADIN1110.
    

    My understanding:
    

      

    • With the SPI command in table 19 the DATA will be transmitted to the FIFO register (if all the other parameters are fine). Using this command muliple times to fill up the FIFO.
      • 

    • Data content sent to the FIFO must be the 2-Byte Header (table 26) and the data for the ethernet frame. (as shown in figure 20 on page 30).
      • 

    • the Transmit over SPE starts as the EOF (End of Frame) is received. The EOF is the IPG (interpacket gap) from the ethernet frame (12 octets with 0x00)
      • 

    

    Is this correct?
    

    And another question:
    What must be exactly inside the frame? Is it the complete ethernet frame including preamble, CRC, etc.? Or only the MAC addresses and the data field itself? 
    Is this somewhere described?
    

    Conditions for the setup:
    Generic SPI
    No CRC (SPI)
    

    Thanks you.
    

    Jürgen
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			








	
	
	
	



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													+1
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
			                            
                        
                on Oct 14, 2022 2:57 PM
            
            
					
      
	
      

		
		
      
					
      Hello Jürgen,
      

      I will try to clarify the transmit process below:
      

      1-. Write the size of the frame in bytes, including the 2-byte header to the MAC transmit frame size register (TX_FSIZE). If the host appended a frame check sequence (FCS) to the frame, this is also included in the size.
      

      2-. Write the data including the 2-byte header to the TX FIFO
      

      3-. Once you have written into the TX FIFO the amount of bytes specified in TX_FSIZE, the transmission begins automatically.
      

      4-. Once the PHY detects that the EOF has been transmitted, the Transmit Ready is asserted and an interrupt triggers if it hasn't been masked; indicating that the transmission has finished and the process can be repeated.
      

      

      You need to write the complete ethernet frame apart from the CRC. There is the option of having the host writing the CRC as well, or having the ADIN1110 to calculate it and append it automatically; this is configured via the CRC_APPEND bitfield in the CONFIG2 register.
      

      Regards,
      

      Raquel
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
						
						
				
				
		
		
      
			
		
      
	
      

      

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													+1
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
			                            
                        
                on Oct 14, 2022 2:57 PM
            
            
					
      
	
      

		
		
      
					
      Hello Jürgen,
      

      I will try to clarify the transmit process below:
      

      1-. Write the size of the frame in bytes, including the 2-byte header to the MAC transmit frame size register (TX_FSIZE). If the host appended a frame check sequence (FCS) to the frame, this is also included in the size.
      

      2-. Write the data including the 2-byte header to the TX FIFO
      

      3-. Once you have written into the TX FIFO the amount of bytes specified in TX_FSIZE, the transmission begins automatically.
      

      4-. Once the PHY detects that the EOF has been transmitted, the Transmit Ready is asserted and an interrupt triggers if it hasn't been masked; indicating that the transmission has finished and the process can be repeated.
      

      

      You need to write the complete ethernet frame apart from the CRC. There is the option of having the host writing the CRC as well, or having the ADIN1110 to calculate it and append it automatically; this is configured via the CRC_APPEND bitfield in the CONFIG2 register.
      

      Regards,
      

      Raquel
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
						
						
				
				
		
		
      
			
		
      
	
      

      

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