Category: Datasheet/Specs
Hello,
I tried to generate 125 MHz frequency in GP_CLK (pin 27), I set GE_CLK_CFG
register (&0xFF1F) to 0x0010 for free clock selection and register GE_IO_GP_CLK_OR_CNTRL (&0xFF3D) to 0x0007 to enable GP_CLK output but i didn't get any output signal.
Is there any configuration missed?
Best Regards,
Nader
[locked by: CatherineR at 11:08 AM (GMT -4) on 28 Mar 2023]
