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[ADIN1300]: No output signal on GP_CLK pin

Category: Datasheet/Specs

Hello,

I tried to generate 125 MHz frequency in GP_CLK (pin 27), I set GE_CLK_CFG
register (&0xFF1F) to 0x0010 for free clock selection and register GE_IO_GP_CLK_OR_CNTRL (&0xFF3D) to 0x0007 to enable GP_CLK output but i didn't get any output signal.
Is there any configuration missed?

Best Regards,
Nader

  • Hi Nadar,

    Could you confirm what your MAC interface selection, PHY Configuration and MDIX Configuration? I can see the clock on the GP_CLK pin on my setup here, I want to make sure I am trying to recreate what you are seeing by doing a like for like comparison with the above mentioned settings.

    Best Regards,

    Mark

  • Hi Mark,

    MAC interface : RGMII RXC/TXC 2 ns Delay

    MDIX: AUTO_MDI_EN (bit10 PHY_CTRL_1 set to 1)

    Best Regard,

    Nader

  • Hi Nader,

     

    Can you confirm the strapping that is used for the PHY Configuration Pins? Or share a schematic?

    Is the part in software power down when you are writing to GE_CLK_CFG?

    Could you export and provide register reads from the GUI?

     

    Regards,

    Mark

  • Hi Mark,

    The GP_CLK line is connected to a 56K pull down resistor, please refer to the schematic in attachment.

    Please find the registers values in attachment.

    Can you clarify more what do you mean by "Is the part in software power down when you are writing to GE_CLK_CFG?" please.

    BR,

    Nader

  • Hi Nader,

     

    I see a problem with your schematic. These resistors values are incorrect compared to the desired settings of MODE4 and MODE4, the pull down is too weak. Judging by the Register reads you provided, the PHY is actually in MODE_2 and MODE_2 for PHY_CFG0 and PHY_CFG1, which is forced 100M Half Duplex, see row number 13 in Table 23 in the ADIN1300 Datasheet. 

    The correct values for Pull Up and Pull Down resistors for the PHY_CFGx pins can be found in Table 19 in the datasheet. Another issue in this area of you schematic is that PHY_CFG0/LED_0 pin is being referenced to the VDDIO power domain, when it should be referenced to the AVDD power domain, see footnote of Table 19 in datasheet. This will also cause issues.

    Is there anything else on the nets of PHY_CFG0 and PHY_CFG1? It looks like there are more connections but I cant see where they go.

    However, this issue alone should not stop you from bringing out the 125MHz Clock on the GP Clock pin. So there must be issues elsewhere, what is the strapping on all of the other strapping pins?

    Also shown from the register reads that you have provided, no link has been established. Was this board intentionally left unconnected? Or can you bring up a link with a Link Partner?

    We can continue this discussion in the private chat you have started if you would like as there seems to be a few issues here.

     

    Regards,

    Mark