Hello!
At speeds of 100/1Gb, the chip works correctly.
When receiving in 10BASE-T mode, a packet arrives with an incorrect preamble on the MAC interface side.
I tried the RGMII and MII interface.
Oscillocope on 10BASE-T:
Oscillocope on 100BASE-TX:
The subsequent part of the packet data is normal.
Hi Hamlet73,
Thank you for getting in contact. Looking at the attached figures the receive side preamble presented by the PHY at the MII MAC interface in 10BASE-T mode is correct according to Figure 22-7 in Clause 22.2.2.8 of IEEE Std 802.3
-2018
Clause 22.2.3.2.2 shows all that is required is that the SFD is received fully and it is correctly aligned at the MII pins. No preamble preceding SFD needs to be conveyed through the MII.
Table 22-4 (and 22-5) defines the requirements for Preamble and SFD reception at the MII per item FS5 in the Protocol Implementation Conformance Statement (PICS) proforma for Clause 22, Reconciliation Sublayer (RS) and Media Independent Interface (MII) In Clause 22.8.
The ADIN1300 is compliant to the standard, and a MAC requiring a full preamble to be presented at the MII is not compliant to the standard. The ADIN1300 does provide the means to set different preamble regeneration options in 10BASE-T mode.
The attached scope capture for 10BASE-T shows the default setting, in which 2 preamble bytes are presented at the MII RX in 10BASE-T mode. To present 7 bytes, GE_B10_REGEN_PRE could be used, which will increase the latency significantly. See below for information on this bit.
Address: 0xFF38, Bit 0
In normal operation the 10BASE-T preamble is consumed while synchronizing 10BASE-T R/X timing and only 1 or 2 bytes of preamble are sent to the MAC. Setting this bit causes the GE sub-system to re-generate a full 10BASE-T preamble.
Best Regards,
Mark
