Q&A - Recent Threads

On ADIN6310 with HSR Redbox configuration - when mac addresses are exchanged between interlink ports - they cannot communicate.

mdejw — Thu, 06 Aug 2026 10:09:03 GMT

EVAL-ADIN6310EBZ, I configure as follows:

```
---------------- HSR status ----------------
type=HSR, end-node=HSR RedBox SAN, device=RedBox, HSR mode=mode H
ports: A=2 (active, up), B=3 (active, up), C=0; interlinks=1,4,5,-1
LRE MAC=02:00:00:2a:0d:33, supervision: A VID=4095 PCP=0, B VID=4095 PCP=0, evaluate=yes, duplicate-time=625
forwarding=store-and-forward
reserved HSR VLAN=4094
HSR counters: TX A=100 B=100 C=37; RX A=90 B=90 C=58
errors: A=0 B=0 C=0; wrong-LAN A=0 B=0
duplicates: unique A=0 B=0; duplicate A=0 B=0; multi A=0 B=0; own RX A=0 B=0
nodes: 1, proxy nodes: 2
HSR node table:
node[1] MAC=02:00:00:cf:c8:42, type=HSR RedBox, last-seen A=15414 B=15414, read-ts=15566
HSR proxy-node table:
proxy[0] MAC=00:e0:4c:38:7d:93
proxy[1] MAC=4c:d7:17:68:b6:9f
proxy[2] read failed: -1
proxy[3] read failed: -1
proxy[4] read failed: -1
proxy[5] read failed: -1
proxy[6] read failed: -1
proxy[7] read failed: -1
-------------- end HSR status --------------

```

As shown, I have connect two Ethernet devices to two interlink ports on one EVAL board (nodes visible in `proxy-node table `). they are connected to ports 4,5. I try arping between them - and I see communication.

```

marcda@marcda-lol:~/PRACA/Q3/Q3-SW-DIAG/repo/zephyr-fw/boards/q3-sw-diag-sim$ arping -b 192.168.44.55
ARPING 192.168.44.55 from 192.168.44.44 enx00e04c387d93
Unicast request from 192.168.44.55 [4C:D7:17:68:B6:9F] 215.684ms
Unicast request from 192.168.44.55 [4C:D7:17:68:B6:9F] 215.528ms
Unicast request from 192.168.44.55 [4C:D7:17:68:B6:9F] 215.637ms
Unicast request from 192.168.44.55 [4C:D7:17:68:B6:9F] 215.622ms
Unicast request from 192.168.44.55 [4C:D7:17:68:B6:9F] 215.636ms
Unicast request from 192.168.44.55 [4C:D7:17:68:B6:9F] 215.530ms
Unicast request from 192.168.44.55 [4C:D7:17:68:B6:9F] 215.613ms
^CSent 7 probes (7 broadcast(s))
Received 7 response(s) (7 request(s))
marcda@marcda-lol:~/PRACA/Q3/Q3-SW-DIAG/repo/zephyr-fw/boards/q3-sw-diag-sim$ ping 192.168.44.55
PING 192.168.44.55 (192.168.44.55) 56(84) bytes of data.
64 bytes from 192.168.44.55: icmp_seq=1 ttl=64 time=457 ms
64 bytes from 192.168.44.55: icmp_seq=2 ttl=64 time=0.803 ms
64 bytes from 192.168.44.55: icmp_seq=3 ttl=64 time=0.746 ms
64 bytes from 192.168.44.55: icmp_seq=4 ttl=64 time=1.01 ms
64 bytes from 192.168.44.55: icmp_seq=5 ttl=64 time=1.39 ms
64 bytes from 192.168.44.55: icmp_seq=6 ttl=64 time=0.950 ms
^C
--- 192.168.44.55 ping statistics ---
6 packets transmitted, 6 received, 0% packet loss, time 5043ms
rtt min/avg/max/mdev = 0.746/76.924/456.651/169.818 ms

```

When I un-pluge one of them and plug to the other port, or I swap them - then there is no communication between them. Waiting more than a minute doesn't change this condition. This seems wrong.

After more than a minut, MAC addresses are still, in `proxy node table`.

```

---------------- HSR status ----------------
type=HSR, end-node=HSR RedBox SAN, device=RedBox, HSR mode=mode H
ports: A=2 (active, up), B=3 (active, up), C=0; interlinks=1,4,5,-1
LRE MAC=02:00:00:2a:0d:33, supervision: A VID=4095 PCP=0, B VID=4095 PCP=0, evaluate=yes, duplicate-time=625
forwarding=store-and-forward
reserved HSR VLAN=4094
HSR counters: TX A=2550 B=2550 C=2703; RX A=1906 B=1906 C=3115
errors: A=0 B=0 C=0; wrong-LAN A=0 B=0
duplicates: unique A=0 B=0; duplicate A=0 B=0; multi A=0 B=0; own RX A=0 B=0
nodes: 1, proxy nodes: 2
HSR node table:
node[1] MAC=02:00:00:cf:c8:42, type=HSR RedBox, last-seen A=475411 B=475411, read-ts=475471
HSR proxy-node table:
proxy[0] MAC=00:e0:4c:38:7d:93
proxy[1] MAC=4c:d7:17:68:b6:9f
proxy[2] read failed: -1
proxy[3] read failed: -1
proxy[4] read failed: -1
proxy[5] read failed: -1
proxy[6] read failed: -1
proxy[7] read failed: -1
-------------- end HSR status --------------

```

When I unplug both ports, and wait till `proxy node table` is cleared, then plug them in. Communication between ports is working. This may be hint in solving this problem.

How to fix this behavior?

Additional question - why reply on broadcast over ADIN6310 configured with HSR takes that long (200+ milliseconds), while using regular Ethernet switch it is less than 2 milliseconds.

Below is ping test over regular Ethernet switch:

```

marcda@marcda-lol:~/PRACA/Q3/Q3-SW-DIAG/repo/zephyr-fw/boards/q3-sw-diag-sim$ arping -b 192.168.44.55
ARPING 192.168.44.55 from 192.168.44.44 enx00e04c387d93
Unicast reply from 192.168.44.55 [4C:D7:17:68:B6:9F] 1.250ms
Unicast reply from 192.168.44.55 [4C:D7:17:68:B6:9F] 1.449ms
Unicast reply from 192.168.44.55 [4C:D7:17:68:B6:9F] 1.385ms
^CSent 3 probes (3 broadcast(s))
Received 3 response(s)
marcda@marcda-lol:~/PRACA/Q3/Q3-SW-DIAG/repo/zephyr-fw/boards/q3-sw-diag-sim$ ping 192.168.44.55
PING 192.168.44.55 (192.168.44.55) 56(84) bytes of data.
64 bytes from 192.168.44.55: icmp_seq=1 ttl=64 time=0.913 ms
64 bytes from 192.168.44.55: icmp_seq=2 ttl=64 time=0.830 ms
64 bytes from 192.168.44.55: icmp_seq=3 ttl=64 time=0.791 ms
^C
--- 192.168.44.55 ping statistics ---
3 packets transmitted, 3 received, 0% packet loss, time 2001ms
rtt min/avg/max/mdev = 0.791/0.844/0.913/0.050 ms
marcda@marcda-lol:~/PRACA/Q3/Q3-SW-DIAG/repo/zephyr-fw/boards/q3-sw-diag-sim$

```

Could you point me a information source that will describe HSR limitations of this switch?

eg:

- maximum number of concurrent connections between interlink MAC port to other HSR MAC addresses..

- limitation on continuously broadcasting MAC addresses connected to HSR ring?

If there is needed some clarification about configuration, I can provide it - or provide wireshark dump from Ethernet configuration interface.

Best regards,

Marcin Dawidowicz

SES AddDevice error -1

subseaSteve — Wed, 05 Aug 2026 19:47:39 GMT

I have successfully configured the EVAL-ADIN6310 board from Windows and now am trying the Linux example-app. The app runs, but returns SES AddDevice error -1. I have built the app on a Beaglebone Black running Debian Trixie. The app and example.xml file are in the same directory. I copied the yang modules from sysrepo-glue-srv to /usr/share/yang/modules/. (Note that without sudo, I get error -602, which I believe indicates the app is unable to access the Ethernet port.)

$ sudo ./ses-example-app -f example-eval-6310.xml -p f4:b8:98:86:3f:bd -i production
Board settings file is located at example-eval-6310.xml
Yang modules folder /usr/share/yang/modules/
libyang[0]: Value "7A" was not found in the dictionary.
libyang[1]: String "7A" not freed from the dictionary, refcount 1
Device MAC: 7A:C6:BB:11:11:11
Init with host MAC: F4:B8:98:86:3f:bd
SES AddDevice error -1

I ran tcpdump and can see activity from the beaglebone but there is no response from the ADIN6310. The board strapping is the same as what works for windows (all jumpers in place except Timer2). Link lights are on at both ends and ifconfig says the link is UP.

$ sudo tcpdump -i eth0 ether proto 0xAAC5 -XX
tcpdump: verbose output suppressed, use -v[v]... for full protocol decode
listening on eth0, link-type EN10MB (Ethernet), snapshot length 262144 bytes
15:31:26.246382 f4:b8:98:86:3f:bd (oui Unknown) > 7a:c6:bb:11:11:11 (oui Unknown), ethertype Unknown (0xaac5), length 60:
0x0000: 7ac6 bb11 1111 f4b8 9886 3fbd aac5 f000 z.........?.....
0x0010: 0000 1900 5600 1400 0100 0000 0900 0000 ....V...........
0x0020: 0800 0000 6800 0000 0200 0000 0000 0000 ....h...........
0x0030: 0000 0000 0000 0000 0000 0000 ............
15:31:27.247781 f4:b8:98:86:3f:bd (oui Unknown) > 7a:c6:bb:ff:fe:00 (oui Unknown), ethertype Unknown (0xaac5), length 60:
0x0000: 7ac6 bbff fe00 f4b8 9886 3fbd aac5 f000 z.........?.....
0x0010: 0000 1900 5600 1400 0200 0000 0900 0000 ....V...........
0x0020: 0800 0000 6800 0000 0200 0000 0000 0000 ....h...........
0x0030: 0000 0000 0000 0000 0000 0000 ............

I see other people were stuck at this same point using SPI, but I am using Ethernet.

Can anyone suggest next steps to troubleshoot? TIA, -Steve

Startup file XML for SFPs

subseaSteve — Tue, 21 Jul 2026 16:27:43 GMT

Can someone point me to the full set of parameters that need to be included in the ADIN6310 startup file to enable 1000BASE-LX SFPs?

I am using the ADIN6310-tsn-evaluation-util on windows. I have modified the startup xml so if-type is sgmii-1000base-sxlx and phy-type is unmanaged. And I have moved the jumpers on the board. Port Status indicates the ports are up and I can see on the port statistics page that packets are being sent, but nothing is received. The far end of the link does not show as being up.

I am guessing this has something to do with LOS polarity. Google search returns the following code snippet. Can sfpEnabled and losPolarity be passed in the <interface> block of the startup file or does this belong somewhere else? Or am I missing something entirely?

TIA,
-Steve

<port>
<portNumber>2</portNumber>
<interfaceMode>SGMII</interfaceMode>
<sfpEnabled>true</sfpEnabled>
<speed>1000</speed>
<losPolarity>active-low</losPolarity>
</port>

Title: ADIN2111 1588 timestamps: t2 - t1 remains constant between two boards with independent 25 MHz crystals

GuoNX — Tue, 14 Jul 2026 03:59:29 GMT

Hi ADI team,

I am using two ADIN2111-based boards connected through the Port 1 10BASE-T1L interface. I am currently trying to bring up a simple IEEE 1588/PTP test over raw Layer-2 Ethernet frames.

I simplified the test to only:

The PTP source sends a PTP Sync frame.
The PTP source reads the ADIN2111 egress timestamp as t1.
The PTP source sends a Follow_Up frame carrying t1.
The PTP receiver receives the Sync frame and obtains the ADIN2111 RX timestamp as t2.
The PTP receiver receives the Follow_Up frame and compares t2 - t1.

There is no Delay_Req/Delay_Resp in this test, and the PTP receiver does not apply any phase correction or frequency correction.

I observed t2 - t1 remains constant between two boards with independent 25 MHz crystals.Here's the details:

Hardware setup

There are two separate boards:

Board A: ADIN2111 used as the PTP source in this test.
Board B: ADIN2111 used as the PTP receiver in this test.
The two boards are connected through ADIN2111 Port 1.
Each ADIN2111 has its own independent 25 MHz crystal source.
The two 25 MHz crystal specifications are approximately ±10 ppm and ±1.5 ppm.
The MCU clocks are also independent from the ADIN2111 25 MHz clock domains.

Because the ADIN2111 25 MHz references are independent, I would expect the free-running 1588 timestamp counters to have a measurable frequency difference over tens or hundreds of seconds, unless some part of the ADIN2111/10BASE-T1L link makes the timestamp counter frequency follow the recovered PHY clock.

Software initialization

Both boards use the ADI ADIN2111 driver with OPEN Alliance SPI.

The initialization flow is approximately:

adin2111_Init(...);
adin2111_Open(...);
adin2111_SetPortEnabled(...);
adin2111_TsEnable(..., ADI_MAC_TS_FORMAT_64B_1588);
adin2111_Enable(...);

The PTP clock wrapper only stores the ADIN2111 device handle:

void myPtpClockInit(adin2111_DeviceHandle_t hDevice)
{
ptpClockDevice = hDevice;
}

The timestamp mode is configured as 64-bit 1588 timestamps. During the test, I dump these registers around the timestamp events.

Typical PTP source register dump:

CONFIG0=0x000080c6
TS_CFG=0x00000001
TS_ADDEND=0x85555555

Typical PTP receiver register dump:

CONFIG0=0x000080e6
TS_CFG=0x00000001
TS_ADDEND=0x85555555

So, on both sides:

CONFIG0.FTSE = 1
CONFIG0.FTSS = 1, 64-bit timestamp format
CONFIG0.SYNC = 1
TS_CFG.TS_EN = 1
TS_ADDEND = 0x85555555, unchanged default value

The difference between 0x80c6 and 0x80e6 appears to be CONFIG0.PROTE, which I do not expect to affect timestamp frequency.

TX timestamp path on the PTP source

The PTP source sends a raw L2 PTP Sync frame with Ethertype 0x88F7. When queueing the Sync frame, I request egress capture A

I wait for the timestamp-ready callback/event before reading the egress timestamp. After the ready event is observed, I call:

adin2111_TsGetEgressTimestamp(
hDevice,
ADI_MAC_EGRESS_CAPTURE_A,
&ts);

This timestamp is used as t1.

Then I build a Follow_Up frame and put this t1 into the Follow_Up payload. I also print the source-side t1.

RX timestamp path on the PTP receiver

On the PTP receiver, when a PTP L2 frame is received, I check the RX buffer descriptor timestamp fields.

The conversion uses:

adin2111_TsConvert(
tsLow,
tsHigh,
ADI_MAC_TS_FORMAT_64B_1588,
&ts);

For a received Sync frame, this converted RX timestamp is used as t2.

For the subsequent Follow_Up frame, the PTP receiver parses t1 from the Follow_Up payload. I verified from logs that the t1 printed by the PTP source and the t1 parsed by the PTP receiver match exactly for all common sequence IDs.

Simplified observation

In this simplified observe-only mode:

Sync is sent once per second.
Follow_Up carries the egress timestamp t1.
The PTP receiver calculates t2 - t1.
The PTP receiver does not send Delay_Req.
The PTP receiver does not call TsSetTimerAbsolute.
The PTP receiver does not modify TS_ADDEND.
No frequency or phase correction is applied.

However, the measured value of t2 - t1 remains essentially constant.

From one log:

106 common Sync/Follow_Up sequence IDs were compared.
The t1 value in the receiver-side Follow_Up matched the source-side printed t1 exactly.
The observed drift of t2 - t1 was only 0 ns or 1 ns over about 100 seconds.
TS_ADDEND remained 0x85555555 on both sides.

This is the surprising part. With two independent 25 MHz crystals, I would expect some visible accumulated phase drift between t1 and t2, for example several microseconds per second for a few ppm difference. But the difference stays constant to around 1 ns.

I also tried heating the receiver-side 25 MHz crystal, but the observed t2 - t1 still did not show meaningful drift.

Questions

1. Is the ADIN2111 1588 timestamp counter always based on the local 25 MHz reference, or can it become frequency-synchronized to the 10BASE-T1L link/PHY recovered clock because of the leader/follower mechanism?

2. Does my TX/RX timestamp usage look correct? The PTP source waits for the Sync egress timestamp-ready event, reads EGRESS_CAPTURE_A as t1, sends t1 in Follow_Up, and the PTP receiver uses the RX buffer descriptor timestamp as t2. If this is the correct method, what could explain t2 - t1 staying constant within about 0/1 ns over ~100 seconds even though the two ADIN2111 devices use independent 25 MHz crystals?

My main concern is that the current result looks too stable for two independent free-running timestamp counters. I would like to understand whether this is expected ADIN2111/10BASE-T1L behavior, or whether I am reading/interpreting the timestamps incorrectly.

Thanks,
GuoNX

Adin3310 only Same data reading

Kowsik — Sat, 20 Jun 2026 05:32:27 GMT

I am currently usnig adin3310 etherenet switch in cusyom board i want too configure it through spi from xazu3eg1sfvc78i i am getting the pulses from the timer0 that there is no image my interrupt is taking that and reading i am getting the read first time the 4 bytes header and the second time header + 20 bytes of the payload but the problem i am not able to read the next data i am countinously reading the same data again ad again i am using the windows example i ported the spi porting layer and replayed the spi function everything is fine but the next reads are not happening i have the spi transactions pdf that i need to get for intilization i am attaching the spi porting layer and the read messages i observed .

Thanks and regards ,

kowsik

/*
 * Copyright (c) 2024 Analog Devices, Inc. All Rights Reserved.
 *
 * This software is proprietary and confidential to Analog Devices, Inc.
 * and its licensors.
 */

/*
 * FreeRTOS Port â€” Zynq UltraScale+ MPSoC (Vitis / FreeRTOS 10)
 * Target  : ADIN3310 Ethernet Switch â€” SPI interface abstraction
 * Toolchain: Xilinx Vitis, arm-none-eabi-gcc
 *
 * Hardware mapping
 * â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€
 *  Windows reference          This port
 *  â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€  â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€
 *  FT4222 USB-SPI bridge      PS-SPI (XSpiPs) on Zynq MPSoC
 *  FT4222 GPIO port 3 (IRQ)   MIO GPIO pin 62  (XGpioPs)
 *  Windows CreateThread()     FreeRTOS xTaskCreate()
 *  WaitForSingleObject(event) FreeRTOS binary semaphore (IRQ â†’ task notify)
 *  HANDLE / BOOL              XSpiPs_Config * / BaseType_t
 *
 * SPI configuration for ADIN3310 (UG2287 Â§3.1)
 *   Mode  : CPOL=0, CPHA=0  (SPI mode 0)
 *   Width : 8-bit
 *   CS    : active-low, driven by hardware (SSNBS)
 *   Max   : 25 MHz â€” use the clock divider appropriate for your PL/PS
 *
 * GPIO / Interrupt
 *   MIO 62 is configured as input with a rising-edge interrupt routed to
 *   GIC via XScuGic.  The ISR posts a binary semaphore; the IRQ task
 *   takes that semaphore and calls HandleReceivedMessage().
 *
 * FreeRTOSConfig.h requirements
 *   configUSE_COUNTING_SEMAPHORES   1
 *   configUSE_TASK_NOTIFICATIONS    1   (optional â€” binary sem used instead)
 *   INCLUDE_vTaskDelete             1
 *   configMAX_PRIORITIES            â‰¥ (SES_PORT_IRQ_TASK_PRIORITY + 1)
 *
 * Vivado / Vitis assumptions
 *   - xparameters.h defines XPAR_PSU_SPI_0_DEVICE_ID / BASEADDR
 *   - xparameters.h defines XPAR_PSU_GPIO_0_DEVICE_ID
 *   - xparameters.h defines XPAR_PSU_GPIO_0_INTR  (GIC SPI ID for GPIO)
 *   - GIC driver (XScuGic) is already initialised by the BSP before
 *     SES_PORT_SPI_Init() is called.
 * â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€
 */

// Includes *******************************************************************

#include <string.h>
#include <stdint.h>
#include <stdio.h>

/* FreeRTOS */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"

/* Xilinx BSP */
#include "xparameters.h"
#include "xspips.h"          /* PS SPI driver                                 */
#include "xgpiops.h"         /* PS GPIO driver                                */
#include "xscugic.h"         /* GIC interrupt controller                      */
#include "xil_exception.h"

/* SES driver */
#include "SES_debug.h"
#include "SES_port_api.h"
#include "SES_PORT_interface.h"
#include "xil_cache.h"
// End Includes ***************************************************************

// Macros, typedefs, enums ****************************************************

/* â”€â”€ General â”€â”€ */
#define SES_PORT_SPI_MAX_TYPE               (15)
#define SES_PORT_SPI_TFER_TYPE_MASK         (0xF)
#define SES_PORT_SEM_INFINITE_WAIT          (-1)

/* Milliseconds the Release path waits for the IRQ task to finish */
#define SES_PORT_SPI_WAIT_THREAD_STOP_MS    (5000U)

/* â”€â”€ SPI frame commands (identical to reference) â”€â”€ */
#define SES_PORT_SPI_READ_CMD               (0x80U)
#define SES_PORT_SPI_WRITE_CMD              (0x40U)
#define SES_PORT_SPI_CMD_SZ                 (1U)

/* â”€â”€ Hardware IDs â”€â”€ pull from xparameters.h; override here if needed â”€â”€ */
#ifndef SES_SPI_DEVICE_ID
#  define SES_SPI_DEVICE_ID                 XPAR_PSU_SPI_0_DEVICE_ID
#endif

#ifndef SES_GPIO_DEVICE_ID
#  define SES_GPIO_DEVICE_ID                XPAR_PSU_GPIO_0_DEVICE_ID
#endif

/* MIO pin used as the ADIN3310 interrupt input */
#define SES_PORT_IRQ_GPIO_PIN               (62U)
#define gpio								(63U)



/*
 * SPI clock divider.
 * PS-SPI ref clock is typically 200 MHz on ZU+.
 * XSPIPS_CLK_PRESCALE_8  â†’ 25 MHz  (ADIN3310 maximum).
 * Adjust if your ref clock differs.
 */
#define SES_SPI_CLK_PRESCALE                XSPIPS_CLK_PRESCALE_32

/* FreeRTOS task parameters for the IRQ handler task */
#define SES_PORT_IRQ_TASK_STACK_WORDS       (1024U)
#define SES_PORT_IRQ_TASK_PRIORITY          (configMAX_PRIORITIES - 1U)
#define SES_PORT_IRQ_TASK_NAME              "SES_SpiIrq"

/* â”€â”€ Struct â”€â”€ */
typedef struct {
    int               initialized;
    void             *spiProtectSem;   /* counting sem, max=1: SPI bus mutex  */
    SemaphoreHandle_t rxEventSem;      /* binary sem: ISR â†’ IRQ task          */
    TaskHandle_t      irqTask;         /* FreeRTOS IRQ handler task           */
    volatile int      stopTask;        /* flag: ask the IRQ task to exit      */
    XSpiPs            spiInst;         /* Xilinx PS-SPI instance              */
    XGpioPs           gpioInst;        /* Xilinx PS-GPIO instance             */
    int               chipSelect;      /* SPI CS index (0 for single-device)  */
} SES_PORT_spiLinkDescription_t;

/* Passed through pvPortMalloc to the IRQ task on creation */
typedef struct {
    int drvHdlIdx;
} SES_PORT_threadData_t;

// End Macros, typedefs, enums ************************************************

// Global Variables ***********************************************************

static SES_PORT_spiLinkDescription_t
    spiLinkDescription_g[SES_PORT_MAX_SPI_LINKS] = { { 0 } };

/* Protects the spiLinkDescription_g[] table during Init/Release */
static void *dataTableProtectionSem_gp = NULL;

/*
 * Shared GIC handle.
 * The application must initialise this before calling SES_PORT_SPI_Init().
 * Declare it extern here so the SPI port can register its GPIO ISR.
 */
extern XScuGic XInterruptController;

// End Global Variables *******************************************************

// Static Function Prototypes *************************************************

static int  GetLinkDescriptionEntry(void);
static int  HandleReceivedMessage(int tblIndex);
static int  InitDrv(int tblIndex);
static int  SpiClose(int tblIndex);
static int  SpiRead(int tblIndex, uint16_t length, uint8_t *dataRx_p);
static void TaskSpiIrq(void *pvParam);
static void GpioIsr(void *callbackRef);

// End Static Function Prototypes *********************************************

// Functions ******************************************************************

/**
 * @brief  Initialise the SPI interface to the ADIN3310.
 *
 * Replaces the Windows FT4222 open/init sequence with XSpiPs + XGpioPs
 * initialisation.  The init parameter struct is SES_PORT_zynqSpiInitParams_t
 * (defined in SES_PORT_interface.h â€” see note in that file).
 *
 * @param[in]  param_p     Pointer to SES_PORT_zynqSpiInitParams_t.
 * @param[out] intfType_p  Set to SES_PORT_spiInterface on success.
 * @param[out] srcMac_p    Not used for SPI; may be NULL.
 *
 * @return  Non-negative interface handle on success, negative error code on failure.
 */
int SES_PORT_SPI_Init(void *param_p,
                      SES_PORT_intfType_t *intfType_p,
                      uint8_t *srcMac_p)
{
    int intfHandle;
    int response;
    SES_PORT_zynqSpiInitParams_t *initParams_p =
        (SES_PORT_zynqSpiInitParams_t *)param_p;

    (void)srcMac_p; /* not used for SPI */

    /* â”€â”€ Parameter check â”€â”€ */
    if ((param_p == NULL) || (intfType_p == NULL)) {
        return SES_PORT_INVALID_PARAM;
    }

    /* â”€â”€ Create the table-protection semaphore once â”€â”€ */
    if (dataTableProtectionSem_gp == NULL) {
        dataTableProtectionSem_gp = SES_PORT_CreateSemaphore(1, 1);
        if (dataTableProtectionSem_gp == NULL) {
            return SES_PORT_ERROR;
        }
    }

    SES_PORT_WaitSemaphore(dataTableProtectionSem_gp,
                           SES_PORT_PROTECTION_TIMEOUT);

    /* â”€â”€ Find a free link-description slot â”€â”€ */
    intfHandle = GetLinkDescriptionEntry();
    if (intfHandle < SES_PORT_OK) {
        SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);
        return SES_PORT_ERROR;
    }

    /* â”€â”€ Per-link SPI-bus mutex (counting sem, max = 1) â”€â”€ */
    spiLinkDescription_g[intfHandle].spiProtectSem =
        SES_PORT_CreateSemaphore(1, 1);
    if (spiLinkDescription_g[intfHandle].spiProtectSem == NULL) {
        SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);
        return SES_PORT_ERROR;
    }

    /*
     * â”€â”€ IRQ event semaphore â”€â”€
     * Binary semaphore:  ISR calls xSemaphoreGiveFromISR(),
     *                    TaskSpiIrq() calls xSemaphoreTake().
     * Replaces the Windows CreateEvent(auto-reset) + WaitForSingleObject().
     */
    spiLinkDescription_g[intfHandle].rxEventSem =
        xSemaphoreCreateBinary();
    if (spiLinkDescription_g[intfHandle].rxEventSem == NULL) {
        SES_PORT_DeleteSemaphore(
            spiLinkDescription_g[intfHandle].spiProtectSem);
        SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);
        return SES_PORT_ERROR;
    }

    /* Store the chip-select index supplied by the caller */
    spiLinkDescription_g[intfHandle].chipSelect = initParams_p->chipSelect;
    spiLinkDescription_g[intfHandle].stopTask   = 0;

    SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);

    /* â”€â”€ Hardware init (SPI + GPIO + IRQ task) â”€â”€ */
    response = InitDrv(intfHandle);
    if (response != SES_PORT_OK) {
        vSemaphoreDelete(spiLinkDescription_g[intfHandle].rxEventSem);
        SES_PORT_DeleteSemaphore(
            spiLinkDescription_g[intfHandle].spiProtectSem);
        return SES_PORT_ERROR;
    }

    spiLinkDescription_g[intfHandle].initialized = 1;
    *intfType_p = SES_PORT_spiInterface;

    return intfHandle;
}

/**
 * @brief  Release (close) the SPI interface.
 *
 * Signals the IRQ task to stop, waits up to SES_PORT_SPI_WAIT_THREAD_STOP_MS,
 * then tears down GPIO, SPI and semaphores.
 */
int SES_PORT_SPI_Release(int intfHandle)
{
    int rv = SES_PORT_OK;

    SES_PORT_WaitSemaphore(dataTableProtectionSem_gp,
                           SES_PORT_PROTECTION_TIMEOUT);

    if (!spiLinkDescription_g[intfHandle].initialized) {
        DBG_INFO("SES_PORT_SPI_Release called before Initialization");
        rv = SES_PORT_NOT_INITIALIZED;
    }

    if (rv == SES_PORT_OK) {
        rv = SpiClose(intfHandle);
        if (rv != SES_PORT_OK) {
            rv = SES_PORT_ERROR;
        }
    }

    SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);

    return rv;
}

/**
 * @brief  Send a framed message to the ADIN3310 over SPI.
 *
 * Prepends the 1-byte WRITE command (0x40) then transfers the full frame
 * using XSpiPs_PolledTransfer() under the protection of the per-link mutex.
 *
 * @param[in] intfHandle  Handle returned by SES_PORT_SPI_Init().
 * @param[in] size        Payload size in bytes (NOT including command byte).
 * @param[in] data_p      Pointer to payload buffer (freed on success).
 *
 * @return SES_PORT_OK on success, negative error code on failure.
 */
int SES_PORT_SPI_SendMessage(int intfHandle, int size, void *data_p)
{
    int      result   = SES_PORT_ERROR;
    int      response = SES_PORT_ERROR;
    int i;
    int      spiFrmSz;
    int      count    = 0;
    int      status;
    uint8_t *tx_frame = NULL;

    /* Dummy RX buffer â€” XSpiPs always full-duplex */
    uint8_t *rx_dummy = NULL;

    if (!spiLinkDescription_g[intfHandle].initialized) {
        return SES_PORT_NOT_INITIALIZED;
    }

    if (data_p == NULL) {
        return SES_PORT_INVALID_PARAM;
    }

    /* Build TX frame: [0x40 | payload] */
    spiFrmSz = size + SES_PORT_SPI_CMD_SZ;

    result = SES_PORT_Malloc((void **)&tx_frame, spiFrmSz);
    if (result != SES_PORT_OK) {
        return SES_PORT_ERROR;
    }

    result = SES_PORT_Malloc((void **)&rx_dummy, spiFrmSz);
    if (result != SES_PORT_OK) {
        SES_PORT_Free(tx_frame);
        return SES_PORT_ERROR;
    }

    tx_frame[0] = SES_PORT_SPI_WRITE_CMD;
    memcpy(tx_frame + SES_PORT_SPI_CMD_SZ, data_p, size);

    /* â”€â”€ Take SPI bus mutex â”€â”€ */
    SES_PORT_WaitSemaphore(spiLinkDescription_g[intfHandle].spiProtectSem,
                           SES_PORT_SEM_INFINITE_WAIT);

    /*
     * XSpiPs_PolledTransfer drives CS automatically when configured with
     * XSPIPS_MANUAL_START_OPTION disabled (the default after SetOptions).
//     */
//    while(1){
    status = XSpiPs_PolledTransfer(
                 &spiLinkDescription_g[intfHandle].spiInst,
                 tx_frame,
                 rx_dummy,
                 (u32)spiFrmSz);
    for(i=0;i<1000;i++);
//    }

    SES_PORT_SignalSemaphore(spiLinkDescription_g[intfHandle].spiProtectSem);

    count = (status == XST_SUCCESS) ? spiFrmSz : 0;

    SES_PORT_Free(tx_frame);
    SES_PORT_Free(rx_dummy);

    if (count != spiFrmSz) {
        response = SES_PORT_ERROR;
    } else {
        response = SES_PORT_OK;
        SES_PORT_Free(data_p);   /* convention: caller's buffer freed on OK */
    }

    return response;
}

/**
 * @brief  Return a human-readable string describing the SPI interface.
 *
 * The FT4222 device enumeration has no equivalent on Zynq; we return a
 * static description based on the BSP parameters instead.
 */
int32_t SES_PORT_SPI_GetInterfaceInfo(char *interfaceInfo_p,
                                      uint16_t bufferSize)
{
    if ((interfaceInfo_p == NULL) || (bufferSize == 0U)) {
        return SES_PORT_BUF_ERR;
    }

    int written = snprintf(interfaceInfo_p, bufferSize,
                           "0,Zynq-UltraScale-PS-SPI(dev=%d,gpio=%d);",
                           (int)SES_SPI_DEVICE_ID,
                           (int)SES_PORT_IRQ_GPIO_PIN);

    return (written > 0) ? SES_PORT_OK : SES_PORT_BUF_ERR;
}

// End Functions **************************************************************

// Static Functions ***********************************************************

/**
 * @brief  Handle one incoming SPI message from the ADIN3310.
 *
 * Reads the 4-byte header, validates the length and transfer-type fields,
 * allocates a receive buffer, reads the payload, then hands everything to
 * SES_ReceiveMessage().  Logic is identical to the Windows reference.
 */
static int HandleReceivedMessage(int tblIndex)
{
    int      response = SES_PORT_OK;
    uint8_t  transferType;
    int16_t  txLength;
    int16_t  pad_to_block;
    uint32_t header   = 0U;
    int      rxLength;
    uint8_t *rx_frame = NULL;

    /* Step 1 â€“ read the 4-byte header */
    response = SpiRead(tblIndex, sizeof(header), (uint8_t *)&header);
    if (response != SES_PORT_OK) {
        return response;
    }

    /* Step 2 â€“ decode and validate length (lower 12 bits) */
    rxLength = (int)((uint16_t)(header & SES_PORT_SPI_LENGTH_MASK));
    if (rxLength != (int)(((~header >> SES_PORT_SPI_INVERTED_LENGTH_SHIFT) &
                           SES_PORT_SPI_LENGTH_MASK))) {
        return SES_PORT_ERROR;
    }

    /* Step 3 â€“ decode and validate transfer type (4 bits) */
    transferType = (uint8_t)((header >> SES_PORT_SPI_TYPE_SHIFT) &
                             SES_PORT_SPI_TFER_TYPE_MASK);
    if (transferType != (uint8_t)(((~header >> SES_PORT_SPI_INVERTED_TYPE_SHIFT) &
                                   SES_PORT_SPI_TFER_TYPE_MASK))) {
        return SES_PORT_ERROR;
    }

    /* Step 4 â€“ round up to block boundary */
    txLength     = (int16_t)(rxLength + SES_PORT_SPI_BLOCK_LENGTH - 1);
    txLength    &= (int16_t)(~(SES_PORT_SPI_BLOCK_LENGTH - 1));
    pad_to_block = txLength - (int16_t)rxLength;

    /* Step 5 â€“ allocate and fill the payload buffer */
    response = SES_PORT_Malloc((void **)&rx_frame,
                               (int)(rxLength + pad_to_block));
    if (response != SES_PORT_OK) {
        return SES_PORT_ERROR;
    }
//pad_to_block
    response = SpiRead(tblIndex, (uint16_t)(rxLength), rx_frame);
    if (response != SES_PORT_OK) {
        (void)SES_PORT_Free(rx_frame);
        return response;
    }

    /* Step 6 â€“ deliver to the SES stack */
    response = SES_ReceiveMessage(tblIndex,
                                  SES_PORT_spiInterface,
                                  rxLength,
                                  (void *)rx_frame,
                                  (-1),
                                  (0),
                                  NULL);
    SES_PORT_Free(rx_frame);
    return response;
}

/**
 * @brief  Initialise the PS-SPI peripheral, GPIO interrupt pin, and IRQ task.
 *
 * Replaces FT_OpenEx / FT4222_SPIMaster_Init / CreateThread.
 */
static int InitDrv(int tblIndex)
{
    int              rv;
    XSpiPs_Config   *spiCfg_p;
    XGpioPs_Config  *gpioCfg_p;
    int              xilStatus;
    SES_PORT_threadData_t *thStruct_p = NULL;
    BaseType_t        taskCreated;

    /* â”€â”€ 1. Initialise PS-SPI â”€â”€ */
    spiCfg_p = XSpiPs_LookupConfig(SES_SPI_DEVICE_ID);
    if (spiCfg_p == NULL) {
        return SES_PORT_ERROR;
    }

    xilStatus = XSpiPs_CfgInitialize(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    spiCfg_p,
                    spiCfg_p->BaseAddress);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /*
     * ADIN3310 SPI: CPOL=0, CPHA=0 (mode 0), 8-bit, MSB first.
     * XSPIPS_MASTER_OPTION   â€“ this device is the SPI master
     * XSPIPS_FORCE_SSELECT_OPTION â€“ hardware drives CS automatically
     *                               (de-asserts after each transfer)
     */
    xilStatus = XSpiPs_SetOptions(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    XSPIPS_MASTER_OPTION |
					XSPIPS_FORCE_SSELECT_OPTION);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    xilStatus = XSpiPs_SetClkPrescaler(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    SES_SPI_CLK_PRESCALE);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /* Select the chip-select line */
    xilStatus = XSpiPs_SetSlaveSelect(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    0x00);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /* â”€â”€ 2. Initialise PS-GPIO for interrupt pin (MIO 62) â”€â”€ */
    gpioCfg_p = XGpioPs_LookupConfig(SES_GPIO_DEVICE_ID);
    if (gpioCfg_p == NULL) {
        return SES_PORT_ERROR;
    }

    xilStatus = XGpioPs_CfgInitialize(
                    &spiLinkDescription_g[tblIndex].gpioInst,
                    gpioCfg_p,
                    gpioCfg_p->BaseAddr);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /* Configure MIO 62 as input */
    XGpioPs_SetDirectionPin(
        &spiLinkDescription_g[tblIndex].gpioInst,
        SES_PORT_IRQ_GPIO_PIN,
        0U);   /* 0 = input */

    /*
     * â”€â”€ 3. Connect GPIO ISR to GIC â”€â”€
     *
     * XPAR_PSU_GPIO_0_INTR is the GIC SPI interrupt ID for the PS GPIO block.
     * All 78 MIO pins share this one GIC line; the ISR reads the interrupt
     * status register to identify which pin fired.
     */
    xilStatus = XScuGic_Connect(
                    &XInterruptController,
                    XPAR_PSU_GPIO_0_INTR,
                    (Xil_ExceptionHandler)GpioIsr,
                    (void *)&spiLinkDescription_g[tblIndex].gpioInst);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /* Rising-edge interrupt on MIO 62 */
    XGpioPs_SetIntrTypePin(
        &spiLinkDescription_g[tblIndex].gpioInst,
        SES_PORT_IRQ_GPIO_PIN,
		XGPIOPS_IRQ_TYPE_EDGE_RISING);//changed to rising edge

    XGpioPs_IntrEnablePin(
        &spiLinkDescription_g[tblIndex].gpioInst,
        SES_PORT_IRQ_GPIO_PIN);

    XScuGic_Enable(&XInterruptController, XPAR_PSU_GPIO_0_INTR);

    /* â”€â”€ 4. Create the IRQ handler task â”€â”€ */
    rv = SES_PORT_Malloc((void **)&thStruct_p,
                         sizeof(SES_PORT_threadData_t));
    if (rv != SES_PORT_OK) {
        return SES_PORT_ERROR;
    }
    thStruct_p->drvHdlIdx = tblIndex;

    /*
     * xTaskCreate() replaces CreateThread().
     * The task runs at the highest priority so interrupt-driven frames are
     * processed before any lower-priority application tasks â€” matching the
     * THREAD_PRIORITY_TIME_CRITICAL setting in the Windows reference.
     */
    taskCreated = xTaskCreate(TaskSpiIrq,
                              SES_PORT_IRQ_TASK_NAME,
                              SES_PORT_IRQ_TASK_STACK_WORDS,
                              (void *)thStruct_p,
                              SES_PORT_IRQ_TASK_PRIORITY,
                              &spiLinkDescription_g[tblIndex].irqTask);

    if (taskCreated != pdPASS) {
        SES_PORT_Free(thStruct_p);
        return SES_PORT_THREAD_FAIL;
    }

    return SES_PORT_OK;
}

/**
 * @brief  Low-level SPI read helper.
 *
 * Prepends the 1-byte READ command (0x80), performs a full-duplex polled
 * transfer, and copies the received payload (skipping the command echo byte)
 * into @p dataRx_p.
 *
 * Block-alignment padding is added on the TX side so the ADIN3310 SPI framing
 * is satisfied (identical calculation to the Windows reference).
 */
static int SpiRead(int tblIndex, uint16_t length, uint8_t *dataRx_p)
{
    int      response = SES_PORT_OK;
    int16_t  txLength;
    int16_t  pad_to_block;
    uint8_t *tx_frame = NULL;
    uint8_t d[22]={0};
    uint8_t *rx_frame = NULL;
//    uint8_t rx_frame[128];
    int      spiFrmSz;
    int      xilStatus;



    /* Round up to block boundary */
    txLength     = (int16_t)(length + SES_PORT_SPI_BLOCK_LENGTH - 1);
    txLength    &= (int16_t)(~(SES_PORT_SPI_BLOCK_LENGTH - 1));
    pad_to_block = txLength - (int16_t)length;

    spiFrmSz = (int)(SES_PORT_SPI_CMD_SZ + length + pad_to_block);



    /* Allocate TX and RX working buffers */
    response = SES_PORT_Malloc((void **)&tx_frame, spiFrmSz);
    if (response != SES_PORT_OK) {
        return SES_PORT_ERROR;
    }
//
    response = SES_PORT_Malloc((void **)&rx_frame, spiFrmSz);
    if (response != SES_PORT_OK) {
        (void)SES_PORT_Free(tx_frame);
        return SES_PORT_ERROR;
    }




    /* Build TX frame: READ command + zero padding */
    tx_frame[0] = SES_PORT_SPI_READ_CMD;
    memset(tx_frame + SES_PORT_SPI_CMD_SZ, 0x00U,
           (size_t)(spiFrmSz - SES_PORT_SPI_CMD_SZ));
//
//    Xil_DCacheFlushRange((INTPTR)tx_frame,(u32)spiFrmSz);
//    Xil_DCacheInvalidateRange((INTPTR)rx_frame,(u32)spiFrmSz);


    /* â”€â”€ Take SPI bus mutex â”€â”€ */
    SES_PORT_WaitSemaphore(spiLinkDescription_g[tblIndex].spiProtectSem,
                           SES_PORT_SEM_INFINITE_WAIT);


    xilStatus = XSpiPs_PolledTransfer(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    tx_frame,
					rx_frame,
                    (u32)spiFrmSz);
    for(int i =0;i<=20;i++){
    	d[i]=rx_frame[i];
    }


//    Xil_DCacheInvalidateRange((INTPTR)rx_frame,(u32)spiFrmSz);

    SES_PORT_SignalSemaphore(spiLinkDescription_g[tblIndex].spiProtectSem);

    if (xilStatus != XST_SUCCESS) {
        response = SES_PORT_ERROR;
    }

    /* Free TX buffer */
    if (SES_PORT_Free(tx_frame) != SES_PORT_OK) {
        (void)SES_PORT_Free(rx_frame);
        return SES_PORT_ERROR;
    }

    /* Copy payload (skip the echoed command byte) into caller's buffer */
    if (response == SES_PORT_OK) {
    	if(length==4){
    	memcpy(dataRx_p, rx_frame+ SES_PORT_SPI_CMD_SZ, length);
    	}
    	else{
    	memcpy(dataRx_p, rx_frame+ SES_PORT_SPI_CMD_SZ+4, length);

    	}

    }
    for(int i =0;i<=20;i++){
    	d[i]=dataRx_p[i];
    }
//
    if (SES_PORT_Free(rx_frame) != SES_PORT_OK) {
        response = SES_PORT_ERROR;
    }

    return response;
}

/**
 * @brief  FreeRTOS IRQ handler task â€” replaces ThreadSpiIrq().
 *
 * Blocks indefinitely on rxEventSem.  The GPIO ISR posts that semaphore
 * whenever MIO 62 sees a rising edge.  On each wake-up the task reads the
 * GPIO pin level and, if still asserted, processes one received message.
 *
 * The task self-deletes when stopTask is set (by SpiClose).
 */
static void TaskSpiIrq(void *pvParam)
{
    SES_PORT_threadData_t  localData;
    SES_PORT_threadData_t *param_p = (SES_PORT_threadData_t *)pvParam;

    /* Copy data locally and free the heap allocation */
    memcpy(&localData, param_p, sizeof(SES_PORT_threadData_t));
    SES_PORT_Free(param_p);

    for (;;) {
        /*
         * Block until GpioIsr posts the semaphore.
         * portMAX_DELAY = wait forever (mirrors INFINITE in the Windows port).
         */
        xSemaphoreTake(
            spiLinkDescription_g[localData.drvHdlIdx].rxEventSem,
            portMAX_DELAY);

        /* Check the exit flag set by SpiClose() */
        if (spiLinkDescription_g[localData.drvHdlIdx].stopTask) {
            break;
        }

        /*
         * Confirm the interrupt pin is still high before reading.
         * Replaces FT4222_GPIO_Read() â€” reads MIO 62 directly.
         */
//        if (XGpioPs_ReadPin(
//                &spiLinkDescription_g[localData.drvHdlIdx].gpioInst,
//                SES_PORT_IRQ_GPIO_PIN) ==1U) {//changed to 0
//            HandleReceivedMessage(localData.drvHdlIdx);
//        }
       while  (XGpioPs_ReadPin(
                   &spiLinkDescription_g[localData.drvHdlIdx].gpioInst,
                   SES_PORT_IRQ_GPIO_PIN) ==1U) {//changed to 0
               HandleReceivedMessage(localData.drvHdlIdx);
           }
    }

    /* Signal SpiClose() that we have exited */
    xSemaphoreGive(
        spiLinkDescription_g[localData.drvHdlIdx].rxEventSem);

    vTaskDelete(NULL);
}

/**
 * @brief  GPIO ISR â€” fires on the rising edge of MIO 62.
 *
 * Clears the interrupt status flag and posts rxEventSem so that TaskSpiIrq
 * wakes up.  Replaces the FT_EVENT_RXCHAR / SetEvent() mechanism.
 *
 * @param callbackRef  Pointer to the XGpioPs instance for this link.
 */
static void GpioIsr(void *callbackRef)
{
    XGpioPs       *gpio_p = (XGpioPs *)callbackRef;
    BaseType_t     xHigherPriorityTaskWoken = pdFALSE;
    u32            pendingIrq;

    /* Read which pins triggered */
    pendingIrq = XGpioPs_IntrGetStatusPin(gpio_p, SES_PORT_IRQ_GPIO_PIN);

    if (pendingIrq) {
        /* Clear the interrupt at the GPIO level */
        XGpioPs_IntrClearPin(gpio_p, SES_PORT_IRQ_GPIO_PIN);

        /*
         * Find the link whose gpioInst matches and post its rxEventSem.
         * In a single-link build this is always index 0; the loop makes
         * it robust for multi-link configurations (SES_PORT_MAX_SPI_LINKS > 1).
         */
        for (int i = 0; i < SES_PORT_MAX_SPI_LINKS; i++) {
            if (spiLinkDescription_g[i].initialized &&
                (&spiLinkDescription_g[i].gpioInst == gpio_p)) {
                xSemaphoreGiveFromISR(
                    spiLinkDescription_g[i].rxEventSem,
                    &xHigherPriorityTaskWoken);
                break;
            }
        }
    }

    /* Yield to a higher-priority task if one was unblocked */
    portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
}

/**
 * @brief  Scan the link-description table for a free slot.
 *
 * @return  Table index on success, -1 if all slots are occupied.
 */
static int GetLinkDescriptionEntry(void)
{
    int i;
    int freeEntry = -1;

    for (i = 0; i < SES_PORT_MAX_SPI_LINKS; i++) {
        if (spiLinkDescription_g[i].initialized == 0) {
            freeEntry = i;
            break;
        }
    }

    return freeEntry;
}

/**
 * @brief  Stop the IRQ task, disable the interrupt, and clean up resources.
 *
 * Replaces the Windows TerminateThread / FT4222_UnInitialize / FT_Close
 * sequence.
 */
static int SpiClose(int tblIndex)
{
    TickType_t waitTicks =
        pdMS_TO_TICKS(SES_PORT_SPI_WAIT_THREAD_STOP_MS);

    if (spiLinkDescription_g[tblIndex].irqTask == NULL) {
        DBG_INFO("SpiClose: invalid task handle");
        return SES_PORT_INVALID_PARAM;
    }

    /* â”€â”€ 1. Ask the IRQ task to exit and wake it up â”€â”€ */
    spiLinkDescription_g[tblIndex].stopTask = 1;
    xSemaphoreGive(spiLinkDescription_g[tblIndex].rxEventSem);

    /*
     * Wait for the task to re-post the semaphore as its exit handshake.
     * If it doesn't respond within the timeout, we give up and return error.
     */
    if (xSemaphoreTake(spiLinkDescription_g[tblIndex].rxEventSem,
                       waitTicks) != pdTRUE) {
        return SES_PORT_ERROR;
    }

    /* â”€â”€ 2. Disable the GPIO interrupt â”€â”€ */
    XGpioPs_IntrDisablePin(
        &spiLinkDescription_g[tblIndex].gpioInst,
        SES_PORT_IRQ_GPIO_PIN);

    XScuGic_Disconnect(&XInterruptController, XPAR_PSU_GPIO_0_INTR);

    /* â”€â”€ 3. Delete the FreeRTOS binary semaphore â”€â”€ */
    vSemaphoreDelete(spiLinkDescription_g[tblIndex].rxEventSem);
    spiLinkDescription_g[tblIndex].rxEventSem = NULL;

    /* â”€â”€ 4. Clear the link-description entry â”€â”€ */
    SES_PORT_WaitSemaphore(spiLinkDescription_g[tblIndex].spiProtectSem,
                           SES_PORT_PROTECTION_TIMEOUT);
    memset(&spiLinkDescription_g[tblIndex], 0,
           sizeof(SES_PORT_spiLinkDescription_t));
    /* NOTE: spiProtectSem is cleared by the memset above; do not signal
     * it after this point.  The SES_PORT_DeleteSemaphore() was called
     * implicitly when the slot was zeroed â€” if your RTOS heap requires
     * explicit deletion, call it before the memset. */

    return SES_PORT_OK;
}

// End Static Functions *******************************************************

ADIN6310 Fails to Calculate Mean Link Delay When Synchronizing with Raspberry Pi CM5 eth0

Katsu717 — Thu, 04 Jun 2026 12:52:31 GMT

Hello！

Hello,

I am trying to synchronize time using IEEE 802.1AS-2020 with a Raspberry Pi CM5 as the Grandmaster(Time Transmitter) and an ADIN6310 as the TimeReceiver.

The Raspberry Pi CM5 is running LinuxPTP (ptp4l), and the ADIN6310 is configured for IEEE 802.1AS-2020 gPTP.

However, synchronization does not complete successfully.

Using Wireshark, I can confirm that the following gPTP messages are being exchanged correctly between the Raspberry Pi CM5 and the ADIN6310:

Announce
Sync
Follow_Up
Pdelay_Req
Pdelay_Resp
Pdelay_Resp_Follow_Up

Despite this, the ADIN6310 never calculates the Mean Link Delay. The Mean Link Delay remains 0 ns, and the device does not achieve synchronization.

One additional observation is that if I replace the Raspberry Pi CM5 eth0 interface with a USB Ethernet adapter, synchronization works correctly and the Mean Link Delay is calculated as expected. The problem only occurs when using the CM5 eth0 interface.

The Raspberry Pi CM5 is running ptp4l with hardware timestamping enabled.

Additional information:

Wireshark confirms that Pdelay_Resp and Pdelay_Resp_Follow_Up messages are exchanged.
On the ADIN6310 status page, the Pdelay timestamp fields (T1–T4) are populated.
However, Mean Link Delay remains 0 ns.
The Parent Dataset shows a Grandmaster Identity of 00-00-00-00-00-00-00-00.
Synchronization succeeds when using a USB Ethernet NIC on the Raspberry Pi, but fails when using the CM5 eth0 interface.

Could there be any known compatibility issues with the Raspberry Pi CM5 Ethernet MAC/PHY and the ADIN6310 gPTP implementation, or any additional settings required for IEEE 802.1AS-2020 interoperability?

Thank you for your help.

↑GUI Candidate screen

↑GUI Status screen

↑ptp4l-configure File

↑ptp4l Execution Results

Device not Responding

Kowsik — Tue, 02 Jun 2026 11:31:04 GMT

Hi,

I am working on the ADIN3310 Industrial Ethernet Switch, for which I have already downloaded the driver from the software resources on the official ADIN3310 website.

I am trying to configure the switch from the Zynq UltraScale+ MPSoC XAZU3EG on my custom board. I have the PS SPI from the Zynq block connected to the Ethernet switch and a GPIO connected to Timer0.

I configured the Zynq block in Vivado by enabling the necessary MIO pins for the SPI signals and a GPIO for the Timer0 interrupts. On power-up, at the Timer0 pin of the Ethernet switch, I am able to see the 1.25 seconds high and 2 ms low signal as mentioned in the user guide.

I generated the bitstream, exported the XSA, and also enabled the TTC for FreeRTOS. I then created a platform project for the XSA in xilfreertos10 instead of standalone. I initialized the driver as mentioned in the user guide and took the Windows example from GitHub, converting the SPI functions and other necessary things to a Vitis FreeRTOS-based implementation.

I am also able to see the data transfer, but in the AddDevice() function, during the CheckMacFirmwareVersion() call, after sending the request, I am getting success. However, I am getting a semaphore timeout error. I also verified the IRQ by putting a breakpoint in the IRQ task, which is being hit, but the SPI read is returning all zeros.

If I bypass the CheckMacFirmwareVersion() call and proceed to SES_InitializePorts(), I still get the same timeout error.

int32_t SES_MX_GetInterfaces(sesID_t sesId,
SES_interfaceDescriptor_t interfaceArray[],
int32_t arrayLength)
{
int rv = SES_PORT_OK;
int32_t retVal = SES_PORT_ERROR;

RPC_sem_t sem = RPC_ReservePoolSem();

rv = SES_GetInterfaces_non_blocking(sesId,
interfaceArray,
arrayLength,
NULL,
sem,
&retVal);
if (rv == SES_PORT_OK) {
// request message sent successfully
rv = SES_PORT_WaitSemaphore(sem, SES_PORT_BLOCK_TIMEOUT)<<<<<<<-------- here i am getting timeout error
if (rv == SES_PORT_TIMEOUT) {
// response timeout/error
retVal = SES_PORT_TIMEOUT;
}
}
else {
retVal = rv;
}

i am also attaching the main ,example_config and spi porting layer for

Thanks and Regards,

K.V.N.S.Kowisk

///////main code 

// Includes *******************************************************************

#include <stdio.h>

/* FreeRTOS */
#include "FreeRTOS.h"
#include "task.h"

/* Xilinx BSP */
#include "xparameters.h"
#include "xscugic.h"
#include "xil_exception.h"

/* SES */
#include "SES_example_config.h"
#include "SES_codes.h"

// End Includes ***************************************************************

// Macros *********************************************************************

/* Application task parameters */
#define SES_APP_TASK_STACK_WORDS    (2048U)
#define SES_APP_TASK_PRIORITY       (tskIDLE_PRIORITY + 1U)
#define SES_APP_TASK_NAME           "SES_App"

// End Macros *****************************************************************

// Global Variables ***********************************************************

/*
 * Single GIC instance shared across the whole application.
 * Declared extern in SES_PORT_SPI_interface.c so the SPI port layer can
 * connect the GPIO ISR without needing a separate init path.
 */
XScuGic XInterruptController;

// End Global Variables *******************************************************

// Static Function Prototypes *************************************************

static void vSesAppTask(void *pvParam);
static int  prvGicInit(void);

// End Static Function Prototypes *********************************************

// Functions ******************************************************************

/**
 * @brief  Zynq/FreeRTOS application entry point.
 *
 * Responsibilities:
 *   1. Initialise the ARM Generic Interrupt Controller (GIC).
 *   2. Enable ARM exceptions so interrupts are routed correctly.
 *   3. Create the SES application task.
 *   4. Start the FreeRTOS scheduler — never returns.
 */
int main(void)
{
    printf("\n--START SES (Zynq FreeRTOS Port)--\n\n");

    /* ── 1. Initialise the GIC ── */
    if (prvGicInit() != XST_SUCCESS) {
        printf("GIC initialisation failed — halting.\n");
        for (;;) {}   /* hang; inspect via debugger */
    }

    /* ── 2. Enable ARM exception handling ── */
    Xil_ExceptionEnable();

    /* ── 3. Create the SES application task ── */
    BaseType_t taskCreated = xTaskCreate(
                                 vSesAppTask,
                                 SES_APP_TASK_NAME,
                                 SES_APP_TASK_STACK_WORDS,
                                 NULL,
                                 SES_APP_TASK_PRIORITY,
                                 NULL);

    if (taskCreated != pdPASS) {
        printf("Failed to create SES app task — halting.\n");
        for (;;) {}
    }

    /* ── 4. Start scheduler — does not return ── */
    vTaskStartScheduler();

    /*
     * Reaching here means the scheduler failed to start (usually because
     * there is not enough heap for the idle task).
     * Check configTOTAL_HEAP_SIZE in FreeRTOSConfig.h.
     */
    printf("Scheduler failed to start — halting.\n");
    for (;;) {}

    return 0;   /* never reached; suppresses compiler warning */
}

// End Functions **************************************************************

// Static Functions ***********************************************************

/**
 * @brief  SES application task — equivalent to the original main() body.
 *
 * Runs AFTER the FreeRTOS scheduler has started.  All SES API calls that
 * create internal FreeRTOS objects (semaphores, tasks) are safe here.
 *
 * The task loops forever at the bottom so FreeRTOS always has at least one
 * user task alive (besides idle and the SES IRQ task).
 */
static void vSesAppTask(void *pvParam)
{
    (void)pvParam;

    /*
     * sesConfig() performs the full hardware + SES library initialisation:
     *   - Opens PS-SPI and XGpioPs (MIO 62)
     *   - Connects the GPIO ISR to the GIC
     *   - Creates the FreeRTOS IRQ handler task (TaskSpiIrq)
     *   - Calls SES_Init(), SES_AddHwInterface(), SES_AddDevice()
     *   - Pushes port configuration to ADIN3310 over SPI
     *
     *
     */
//    sesGetAppInfo_Example();

    if (SES_OK == sesConfig()) {

        /* Print ADIN3310 firmware version over SPI */
        sesGetAppInfo_Example();

        printf("############ Configuring the Switch ###################\n");

        /*
         * Run whichever protocol examples are enabled by compile-time flags
         * (TIME_SYNC, MSTP, FRER, LLDP_INIT, etc.).
         * This function may block in the interactive TIME_SYNC loop —
         * that is fine because TaskSpiIrq runs at a higher priority and
         * will still process incoming frames while this task is in scanf().
         */
        sesProtocolInitialization_Example();

    } else {
        printf("SES initialisation failed !!!!\n");
    }

    printf("\n--END--\n");

    /*
     * Keep the task alive.
     * Deleting the task here (vTaskDelete(NULL)) would be valid only if you
     * are certain no more SES callbacks will need this task's stack.
     * Blocking on a long delay is the safe default.
     */
    for (;;) {
        vTaskDelay(pdMS_TO_TICKS(1000));
    }
}

/**
 * @brief  Initialise the ARM Generic Interrupt Controller.
 *
 * Uses the single XScuGic instance (xInterruptController) that is shared
 * with SES_PORT_SPI_interface.c via the extern declaration there.
 *
 * @return XST_SUCCESS on success, XST_FAILURE on error.
 */
static int prvGicInit(void)
{
    XScuGic_Config *gicCfg_p;
    int             status;

    /* Look up the GIC hardware configuration from xparameters.h */
    gicCfg_p = XScuGic_LookupConfig(XPAR_PSU_ACPU_GIC_DEVICE_ID);
    if (gicCfg_p == NULL) {
        return XST_FAILURE;
    }

    /* Initialise the GIC driver */
    status = XScuGic_CfgInitialize(&XInterruptController,
                                   gicCfg_p,
                                   gicCfg_p->CpuBaseAddress);
    if (status != XST_SUCCESS) {
        return XST_FAILURE;
    }

    /*
     * Connect the GIC interrupt handler to the ARM exception vector.
     * After this, any peripheral that raises a GIC SPI interrupt will be
     * routed through XScuGic_InterruptHandler automatically.
     */
    Xil_ExceptionRegisterHandler(
        XIL_EXCEPTION_ID_INT,
        (Xil_ExceptionHandler)XScuGic_InterruptHandler,
        &XInterruptController);

    return XST_SUCCESS;
}

// End Static Functions *******************************************************




////////ses_port_spi_interface


#include <string.h>
#include <stdint.h>
#include <stdio.h>

/* FreeRTOS */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"

/* Xilinx BSP */
#include "xparameters.h"
#include "xspips.h"          /* PS SPI driver                                 */
#include "xgpiops.h"         /* PS GPIO driver                                */
#include "xscugic.h"         /* GIC interrupt controller                      */
#include "xil_exception.h"

/* SES driver */
#include "SES_debug.h"
#include "SES_port_api.h"
#include "SES_PORT_interface.h"

// End Includes ***************************************************************

// Macros, typedefs, enums ****************************************************

/* ── General ── */
#define SES_PORT_SPI_MAX_TYPE               (15)
#define SES_PORT_SPI_TFER_TYPE_MASK         (0xF)
#define SES_PORT_SEM_INFINITE_WAIT          (-1)

/* Milliseconds the Release path waits for the IRQ task to finish */
#define SES_PORT_SPI_WAIT_THREAD_STOP_MS    (5000U)

/* ── SPI frame commands (identical to reference) ── */
#define SES_PORT_SPI_READ_CMD               (0x80U)
#define SES_PORT_SPI_WRITE_CMD              (0x40U)
#define SES_PORT_SPI_CMD_SZ                 (1U)

/* ── Hardware IDs ── pull from xparameters.h; override here if needed ── */
#ifndef SES_SPI_DEVICE_ID
#  define SES_SPI_DEVICE_ID                 XPAR_PSU_SPI_0_DEVICE_ID
#endif

#ifndef SES_GPIO_DEVICE_ID
#  define SES_GPIO_DEVICE_ID                XPAR_PSU_GPIO_0_DEVICE_ID
#endif

/* MIO pin used as the ADIN3310 interrupt input */
#define SES_PORT_IRQ_GPIO_PIN               (62U)
#define gpio								(63U)

/*
 * SPI clock divider.
 * PS-SPI ref clock is typically 200 MHz on ZU+.
 * XSPIPS_CLK_PRESCALE_8  → 25 MHz  (ADIN3310 maximum).
 * Adjust if your ref clock differs.
 */
#define SES_SPI_CLK_PRESCALE                XSPIPS_CLK_PRESCALE_8

/* FreeRTOS task parameters for the IRQ handler task */
#define SES_PORT_IRQ_TASK_STACK_WORDS       (1024U)
#define SES_PORT_IRQ_TASK_PRIORITY          (configMAX_PRIORITIES - 1U)
#define SES_PORT_IRQ_TASK_NAME              "SES_SpiIrq"

/* ── Struct ── */
typedef struct {
    int               initialized;
    void             *spiProtectSem;   /* counting sem, max=1: SPI bus mutex  */
    SemaphoreHandle_t rxEventSem;      /* binary sem: ISR → IRQ task          */
    TaskHandle_t      irqTask;         /* FreeRTOS IRQ handler task           */
    volatile int      stopTask;        /* flag: ask the IRQ task to exit      */
    XSpiPs            spiInst;         /* Xilinx PS-SPI instance              */
    XGpioPs           gpioInst;        /* Xilinx PS-GPIO instance             */
    int               chipSelect;      /* SPI CS index (0 for single-device)  */
} SES_PORT_spiLinkDescription_t;

/* Passed through pvPortMalloc to the IRQ task on creation */
typedef struct {
    int drvHdlIdx;
} SES_PORT_threadData_t;

// End Macros, typedefs, enums ************************************************

// Global Variables ***********************************************************

static SES_PORT_spiLinkDescription_t
    spiLinkDescription_g[SES_PORT_MAX_SPI_LINKS] = { { 0 } };

/* Protects the spiLinkDescription_g[] table during Init/Release */
static void *dataTableProtectionSem_gp = NULL;

/*
 * Shared GIC handle.
 * The application must initialise this before calling SES_PORT_SPI_Init().
 * Declare it extern here so the SPI port can register its GPIO ISR.
 */
extern XScuGic XInterruptController;

// End Global Variables *******************************************************

// Static Function Prototypes *************************************************

static int  GetLinkDescriptionEntry(void);
static int  HandleReceivedMessage(int tblIndex);
static int  InitDrv(int tblIndex);
static int  SpiClose(int tblIndex);
static int  SpiRead(int tblIndex, uint16_t length, uint8_t *dataRx_p);
static void TaskSpiIrq(void *pvParam);
static void GpioIsr(void *callbackRef);

// End Static Function Prototypes *********************************************

// Functions ******************************************************************

/**
 * @brief  Initialise the SPI interface to the ADIN3310.
 *
 * Replaces the Windows FT4222 open/init sequence with XSpiPs + XGpioPs
 * initialisation.  The init parameter struct is SES_PORT_zynqSpiInitParams_t
 * (defined in SES_PORT_interface.h — see note in that file).
 *
 * @param[in]  param_p     Pointer to SES_PORT_zynqSpiInitParams_t.
 * @param[out] intfType_p  Set to SES_PORT_spiInterface on success.
 * @param[out] srcMac_p    Not used for SPI; may be NULL.
 *
 * @return  Non-negative interface handle on success, negative error code on failure.
 */
int SES_PORT_SPI_Init(void *param_p,
                      SES_PORT_intfType_t *intfType_p,
                      uint8_t *srcMac_p)
{
    int intfHandle;
    int response;
    SES_PORT_zynqSpiInitParams_t *initParams_p =
        (SES_PORT_zynqSpiInitParams_t *)param_p;

    (void)srcMac_p; /* not used for SPI */

    /* ── Parameter check ── */
    if ((param_p == NULL) || (intfType_p == NULL)) {
        return SES_PORT_INVALID_PARAM;
    }

    /* ── Create the table-protection semaphore once ── */
    if (dataTableProtectionSem_gp == NULL) {
        dataTableProtectionSem_gp = SES_PORT_CreateSemaphore(1, 1);
        if (dataTableProtectionSem_gp == NULL) {
            return SES_PORT_ERROR;
        }
    }

    SES_PORT_WaitSemaphore(dataTableProtectionSem_gp,
                           SES_PORT_PROTECTION_TIMEOUT);

    /* ── Find a free link-description slot ── */
    intfHandle = GetLinkDescriptionEntry();
    if (intfHandle < SES_PORT_OK) {
        SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);
        return SES_PORT_ERROR;
    }

    /* ── Per-link SPI-bus mutex (counting sem, max = 1) ── */
    spiLinkDescription_g[intfHandle].spiProtectSem =
        SES_PORT_CreateSemaphore(1, 1);
    if (spiLinkDescription_g[intfHandle].spiProtectSem == NULL) {
        SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);
        return SES_PORT_ERROR;
    }

    /*
     * ── IRQ event semaphore ──
     * Binary semaphore:  ISR calls xSemaphoreGiveFromISR(),
     *                    TaskSpiIrq() calls xSemaphoreTake().
     * Replaces the Windows CreateEvent(auto-reset) + WaitForSingleObject().
     */
    spiLinkDescription_g[intfHandle].rxEventSem =
        xSemaphoreCreateBinary();
    if (spiLinkDescription_g[intfHandle].rxEventSem == NULL) {
        SES_PORT_DeleteSemaphore(
            spiLinkDescription_g[intfHandle].spiProtectSem);
        SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);
        return SES_PORT_ERROR;
    }

    /* Store the chip-select index supplied by the caller */
    spiLinkDescription_g[intfHandle].chipSelect = initParams_p->chipSelect;
    spiLinkDescription_g[intfHandle].stopTask   = 0;

    SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);

    /* ── Hardware init (SPI + GPIO + IRQ task) ── */
    response = InitDrv(intfHandle);
    if (response != SES_PORT_OK) {
        vSemaphoreDelete(spiLinkDescription_g[intfHandle].rxEventSem);
        SES_PORT_DeleteSemaphore(
            spiLinkDescription_g[intfHandle].spiProtectSem);
        return SES_PORT_ERROR;
    }

    spiLinkDescription_g[intfHandle].initialized = 1;
    *intfType_p = SES_PORT_spiInterface;

    return intfHandle;
}

/**
 * @brief  Release (close) the SPI interface.
 *
 * Signals the IRQ task to stop, waits up to SES_PORT_SPI_WAIT_THREAD_STOP_MS,
 * then tears down GPIO, SPI and semaphores.
 */
int SES_PORT_SPI_Release(int intfHandle)
{
    int rv = SES_PORT_OK;

    SES_PORT_WaitSemaphore(dataTableProtectionSem_gp,
                           SES_PORT_PROTECTION_TIMEOUT);

    if (!spiLinkDescription_g[intfHandle].initialized) {
        DBG_INFO("SES_PORT_SPI_Release called before Initialization");
        rv = SES_PORT_NOT_INITIALIZED;
    }

    if (rv == SES_PORT_OK) {
        rv = SpiClose(intfHandle);
        if (rv != SES_PORT_OK) {
            rv = SES_PORT_ERROR;
        }
    }

    SES_PORT_SignalSemaphore(dataTableProtectionSem_gp);

    return rv;
}

/**
 * @brief  Send a framed message to the ADIN3310 over SPI.
 *
 * Prepends the 1-byte WRITE command (0x40) then transfers the full frame
 * using XSpiPs_PolledTransfer() under the protection of the per-link mutex.
 *
 * @param[in] intfHandle  Handle returned by SES_PORT_SPI_Init().
 * @param[in] size        Payload size in bytes (NOT including command byte).
 * @param[in] data_p      Pointer to payload buffer (freed on success).
 *
 * @return SES_PORT_OK on success, negative error code on failure.
 */
int SES_PORT_SPI_SendMessage(int intfHandle, int size, void *data_p)
{
    int      result   = SES_PORT_ERROR;
    int      response = SES_PORT_ERROR;
    int i;
    int      spiFrmSz;
    int      count    = 0;
    int      status;
    uint8_t *tx_frame = NULL;

    /* Dummy RX buffer — XSpiPs always full-duplex */
    uint8_t *rx_dummy = NULL;

    if (!spiLinkDescription_g[intfHandle].initialized) {
        return SES_PORT_NOT_INITIALIZED;
    }

    if (data_p == NULL) {
        return SES_PORT_INVALID_PARAM;
    }

    /* Build TX frame: [0x40 | payload] */
    spiFrmSz = size + SES_PORT_SPI_CMD_SZ;

    result = SES_PORT_Malloc((void **)&tx_frame, spiFrmSz);
    if (result != SES_PORT_OK) {
        return SES_PORT_ERROR;
    }

    result = SES_PORT_Malloc((void **)&rx_dummy, spiFrmSz);
    if (result != SES_PORT_OK) {
        SES_PORT_Free(tx_frame);
        return SES_PORT_ERROR;
    }

    tx_frame[0] = SES_PORT_SPI_WRITE_CMD;
    memcpy(tx_frame + SES_PORT_SPI_CMD_SZ, data_p, size);

    /* ── Take SPI bus mutex ── */
    SES_PORT_WaitSemaphore(spiLinkDescription_g[intfHandle].spiProtectSem,
                           SES_PORT_SEM_INFINITE_WAIT);

    /*
     * XSpiPs_PolledTransfer drives CS automatically when configured with
     * XSPIPS_MANUAL_START_OPTION disabled (the default after SetOptions).
//     */
//    while(1){
    status = XSpiPs_PolledTransfer(
                 &spiLinkDescription_g[intfHandle].spiInst,
                 tx_frame,
                 rx_dummy,
                 (u32)spiFrmSz);
//    for(i=0;i<1000;i++);
//    }

    SES_PORT_SignalSemaphore(spiLinkDescription_g[intfHandle].spiProtectSem);

    count = (status == XST_SUCCESS) ? spiFrmSz : 0;

    SES_PORT_Free(tx_frame);
    SES_PORT_Free(rx_dummy);

    if (count != spiFrmSz) {
        response = SES_PORT_ERROR;
    } else {
        response = SES_PORT_OK;
        SES_PORT_Free(data_p);   /* convention: caller's buffer freed on OK */
    }

    return response;
}

/**
 * @brief  Return a human-readable string describing the SPI interface.
 *
 * The FT4222 device enumeration has no equivalent on Zynq; we return a
 * static description based on the BSP parameters instead.
 */
int32_t SES_PORT_SPI_GetInterfaceInfo(char *interfaceInfo_p,
                                      uint16_t bufferSize)
{
    if ((interfaceInfo_p == NULL) || (bufferSize == 0U)) {
        return SES_PORT_BUF_ERR;
    }

    int written = snprintf(interfaceInfo_p, bufferSize,
                           "0,Zynq-UltraScale-PS-SPI(dev=%d,gpio=%d);",
                           (int)SES_SPI_DEVICE_ID,
                           (int)SES_PORT_IRQ_GPIO_PIN);

    return (written > 0) ? SES_PORT_OK : SES_PORT_BUF_ERR;
}

// End Functions **************************************************************

// Static Functions ***********************************************************

/**
 * @brief  Handle one incoming SPI message from the ADIN3310.
 *
 * Reads the 4-byte header, validates the length and transfer-type fields,
 * allocates a receive buffer, reads the payload, then hands everything to
 * SES_ReceiveMessage().  Logic is identical to the Windows reference.
 */
static int HandleReceivedMessage(int tblIndex)
{
    int      response = SES_PORT_OK;
    uint8_t  transferType;
    int16_t  txLength;
    int16_t  pad_to_block;
    uint32_t header   = 0U;
    int      rxLength;
    uint8_t *rx_frame = NULL;

    /* Step 1 – read the 4-byte header */
    response = SpiRead(tblIndex, sizeof(header), (uint8_t *)&header);
    if (response != SES_PORT_OK) {
        return response;
    }

    /* Step 2 – decode and validate length (lower 12 bits) */
    rxLength = (int)((uint16_t)(header & SES_PORT_SPI_LENGTH_MASK));
    if (rxLength != (int)(((~header >> SES_PORT_SPI_INVERTED_LENGTH_SHIFT) &
                           SES_PORT_SPI_LENGTH_MASK))) {
        return SES_PORT_ERROR;
    }

    /* Step 3 – decode and validate transfer type (4 bits) */
    transferType = (uint8_t)((header >> SES_PORT_SPI_TYPE_SHIFT) &
                             SES_PORT_SPI_TFER_TYPE_MASK);
    if (transferType != (uint8_t)(((~header >> SES_PORT_SPI_INVERTED_TYPE_SHIFT) &
                                   SES_PORT_SPI_TFER_TYPE_MASK))) {
        return SES_PORT_ERROR;
    }

    /* Step 4 – round up to block boundary */
    txLength     = (int16_t)(rxLength + SES_PORT_SPI_BLOCK_LENGTH - 1);
    txLength    &= (int16_t)(~(SES_PORT_SPI_BLOCK_LENGTH - 1));
    pad_to_block = txLength - (int16_t)rxLength;

    /* Step 5 – allocate and fill the payload buffer */
    response = SES_PORT_Malloc((void **)&rx_frame,
                               (int)(rxLength + pad_to_block));
    if (response != SES_PORT_OK) {
        return SES_PORT_ERROR;
    }

    response = SpiRead(tblIndex, (uint16_t)(rxLength + pad_to_block), rx_frame);
    if (response != SES_PORT_OK) {
        (void)SES_PORT_Free(rx_frame);
        return response;
    }

    /* Step 6 – deliver to the SES stack */
    response = SES_ReceiveMessage(tblIndex,
                                  SES_PORT_spiInterface,
                                  rxLength,
                                  (void *)rx_frame,
                                  (-1),
                                  (0),
                                  NULL);
    SES_PORT_Free(rx_frame);
    return response;
}

/**
 * @brief  Initialise the PS-SPI peripheral, GPIO interrupt pin, and IRQ task.
 *
 * Replaces FT_OpenEx / FT4222_SPIMaster_Init / CreateThread.
 */
static int InitDrv(int tblIndex)
{
    int              rv;
    XSpiPs_Config   *spiCfg_p;
    XGpioPs_Config  *gpioCfg_p;
    int              xilStatus;
    SES_PORT_threadData_t *thStruct_p = NULL;
    BaseType_t        taskCreated;

    /* ── 1. Initialise PS-SPI ── */
    spiCfg_p = XSpiPs_LookupConfig(SES_SPI_DEVICE_ID);
    if (spiCfg_p == NULL) {
        return SES_PORT_ERROR;
    }

    xilStatus = XSpiPs_CfgInitialize(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    spiCfg_p,
                    spiCfg_p->BaseAddress);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /*
     * ADIN3310 SPI: CPOL=0, CPHA=0 (mode 0), 8-bit, MSB first.
     * XSPIPS_MASTER_OPTION   – this device is the SPI master
     * XSPIPS_FORCE_SSELECT_OPTION – hardware drives CS automatically
     *                               (de-asserts after each transfer)
     */
    xilStatus = XSpiPs_SetOptions(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    XSPIPS_MASTER_OPTION |
                    XSPIPS_FORCE_SSELECT_OPTION);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    xilStatus = XSpiPs_SetClkPrescaler(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    SES_SPI_CLK_PRESCALE);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /* Select the chip-select line */
    xilStatus = XSpiPs_SetSlaveSelect(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    (u8)spiLinkDescription_g[tblIndex].chipSelect);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /* ── 2. Initialise PS-GPIO for interrupt pin (MIO 62) ── */
    gpioCfg_p = XGpioPs_LookupConfig(SES_GPIO_DEVICE_ID);
    if (gpioCfg_p == NULL) {
        return SES_PORT_ERROR;
    }

    xilStatus = XGpioPs_CfgInitialize(
                    &spiLinkDescription_g[tblIndex].gpioInst,
                    gpioCfg_p,
                    gpioCfg_p->BaseAddr);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /* Configure MIO 62 as input */
    XGpioPs_SetDirectionPin(
        &spiLinkDescription_g[tblIndex].gpioInst,
        SES_PORT_IRQ_GPIO_PIN,
        0U);   /* 0 = input */

    /*
     * ── 3. Connect GPIO ISR to GIC ──
     *
     * XPAR_PSU_GPIO_0_INTR is the GIC SPI interrupt ID for the PS GPIO block.
     * All 78 MIO pins share this one GIC line; the ISR reads the interrupt
     * status register to identify which pin fired.
     */
    xilStatus = XScuGic_Connect(
                    &XInterruptController,
                    XPAR_PSU_GPIO_0_INTR,
                    (Xil_ExceptionHandler)GpioIsr,
                    (void *)&spiLinkDescription_g[tblIndex].gpioInst);
    if (xilStatus != XST_SUCCESS) {
        return SES_PORT_ERROR;
    }

    /* Rising-edge interrupt on MIO 62 */
    XGpioPs_SetIntrTypePin(
        &spiLinkDescription_g[tblIndex].gpioInst,
        SES_PORT_IRQ_GPIO_PIN,
        XGPIOPS_IRQ_TYPE_EDGE_RISING);

    XGpioPs_IntrEnablePin(
        &spiLinkDescription_g[tblIndex].gpioInst,
        SES_PORT_IRQ_GPIO_PIN);

    XScuGic_Enable(&XInterruptController, XPAR_PSU_GPIO_0_INTR);

    /* ── 4. Create the IRQ handler task ── */
    rv = SES_PORT_Malloc((void **)&thStruct_p,
                         sizeof(SES_PORT_threadData_t));
    if (rv != SES_PORT_OK) {
        return SES_PORT_ERROR;
    }
    thStruct_p->drvHdlIdx = tblIndex;

    /*
     * xTaskCreate() replaces CreateThread().
     * The task runs at the highest priority so interrupt-driven frames are
     * processed before any lower-priority application tasks — matching the
     * THREAD_PRIORITY_TIME_CRITICAL setting in the Windows reference.
     */
    taskCreated = xTaskCreate(TaskSpiIrq,
                              SES_PORT_IRQ_TASK_NAME,
                              SES_PORT_IRQ_TASK_STACK_WORDS,
                              (void *)thStruct_p,
                              SES_PORT_IRQ_TASK_PRIORITY,
                              &spiLinkDescription_g[tblIndex].irqTask);

    if (taskCreated != pdPASS) {
        SES_PORT_Free(thStruct_p);
        return SES_PORT_THREAD_FAIL;
    }

    return SES_PORT_OK;
}

/**
 * @brief  Low-level SPI read helper.
 *
 * Prepends the 1-byte READ command (0x80), performs a full-duplex polled
 * transfer, and copies the received payload (skipping the command echo byte)
 * into @p dataRx_p.
 *
 * Block-alignment padding is added on the TX side so the ADIN3310 SPI framing
 * is satisfied (identical calculation to the Windows reference).
 */
static int SpiRead(int tblIndex, uint16_t length, uint8_t *dataRx_p)
{
    int      response = SES_PORT_OK;
    int16_t  txLength;
    int16_t  pad_to_block;
    uint8_t *tx_frame = NULL;
    uint8_t *rx_frame = NULL;
    int      spiFrmSz;
    int      xilStatus;

    /* Round up to block boundary */
    txLength     = (int16_t)(length + SES_PORT_SPI_BLOCK_LENGTH - 1);
    txLength    &= (int16_t)(~(SES_PORT_SPI_BLOCK_LENGTH - 1));
    pad_to_block = txLength - (int16_t)length;

    spiFrmSz = (int)(SES_PORT_SPI_CMD_SZ + length + pad_to_block);

    /* Allocate TX and RX working buffers */
    response = SES_PORT_Malloc((void **)&tx_frame, spiFrmSz);
    if (response != SES_PORT_OK) {
        return SES_PORT_ERROR;
    }

    response = SES_PORT_Malloc((void **)&rx_frame, spiFrmSz);
    if (response != SES_PORT_OK) {
        (void)SES_PORT_Free(tx_frame);
        return SES_PORT_ERROR;
    }

    /* Build TX frame: READ command + zero padding */
    tx_frame[0] = SES_PORT_SPI_READ_CMD;
    memset(tx_frame + SES_PORT_SPI_CMD_SZ, 0x00U,
           (size_t)(spiFrmSz - SES_PORT_SPI_CMD_SZ));

    /* ── Take SPI bus mutex ── */
    SES_PORT_WaitSemaphore(spiLinkDescription_g[tblIndex].spiProtectSem,
                           SES_PORT_SEM_INFINITE_WAIT);

    xilStatus = XSpiPs_PolledTransfer(
                    &spiLinkDescription_g[tblIndex].spiInst,
                    tx_frame,
                    rx_frame,
                    (u32)spiFrmSz);

    SES_PORT_SignalSemaphore(spiLinkDescription_g[tblIndex].spiProtectSem);

    if (xilStatus != XST_SUCCESS) {
        response = SES_PORT_ERROR;
    }

    /* Free TX buffer */
    if (SES_PORT_Free(tx_frame) != SES_PORT_OK) {
        (void)SES_PORT_Free(rx_frame);
        return SES_PORT_ERROR;
    }

    /* Copy payload (skip the echoed command byte) into caller's buffer */
    if (response == SES_PORT_OK) {
        memcpy(dataRx_p, rx_frame + SES_PORT_SPI_CMD_SZ, length);
    }

    if (SES_PORT_Free(rx_frame) != SES_PORT_OK) {
        response = SES_PORT_ERROR;
    }

    return response;
}

/**
 * @brief  FreeRTOS IRQ handler task — replaces ThreadSpiIrq().
 *
 * Blocks indefinitely on rxEventSem.  The GPIO ISR posts that semaphore
 * whenever MIO 62 sees a rising edge.  On each wake-up the task reads the
 * GPIO pin level and, if still asserted, processes one received message.
 *
 * The task self-deletes when stopTask is set (by SpiClose).
 */
static void TaskSpiIrq(void *pvParam)
{
    SES_PORT_threadData_t  localData;
    SES_PORT_threadData_t *param_p = (SES_PORT_threadData_t *)pvParam;

    /* Copy data locally and free the heap allocation */
    memcpy(&localData, param_p, sizeof(SES_PORT_threadData_t));
    SES_PORT_Free(param_p);

    for (;;) {
        /*
         * Block until GpioIsr posts the semaphore.
         * portMAX_DELAY = wait forever (mirrors INFINITE in the Windows port).
         */
        xSemaphoreTake(
            spiLinkDescription_g[localData.drvHdlIdx].rxEventSem,
            portMAX_DELAY);

        /* Check the exit flag set by SpiClose() */
        if (spiLinkDescription_g[localData.drvHdlIdx].stopTask) {
            break;
        }

        /*
         * Confirm the interrupt pin is still high before reading.
         * Replaces FT4222_GPIO_Read() — reads MIO 62 directly.
         */
        if (XGpioPs_ReadPin(
                &spiLinkDescription_g[localData.drvHdlIdx].gpioInst,
                SES_PORT_IRQ_GPIO_PIN) == 1U) {
            HandleReceivedMessage(localData.drvHdlIdx);
        }
    }

    /* Signal SpiClose() that we have exited */
    xSemaphoreGive(
        spiLinkDescription_g[localData.drvHdlIdx].rxEventSem);

    vTaskDelete(NULL);
}

/**
 * @brief  GPIO ISR — fires on the rising edge of MIO 62.
 *
 * Clears the interrupt status flag and posts rxEventSem so that TaskSpiIrq
 * wakes up.  Replaces the FT_EVENT_RXCHAR / SetEvent() mechanism.
 *
 * @param callbackRef  Pointer to the XGpioPs instance for this link.
 */
static void GpioIsr(void *callbackRef)
{
    XGpioPs       *gpio_p = (XGpioPs *)callbackRef;
    BaseType_t     xHigherPriorityTaskWoken = pdFALSE;
    u32            pendingIrq;

    /* Read which pins triggered */
    pendingIrq = XGpioPs_IntrGetStatusPin(gpio_p, SES_PORT_IRQ_GPIO_PIN);

    if (pendingIrq) {
        /* Clear the interrupt at the GPIO level */
        XGpioPs_IntrClearPin(gpio_p, SES_PORT_IRQ_GPIO_PIN);

        /*
         * Find the link whose gpioInst matches and post its rxEventSem.
         * In a single-link build this is always index 0; the loop makes
         * it robust for multi-link configurations (SES_PORT_MAX_SPI_LINKS > 1).
         */
        for (int i = 0; i < SES_PORT_MAX_SPI_LINKS; i++) {
            if (spiLinkDescription_g[i].initialized &&
                (&spiLinkDescription_g[i].gpioInst == gpio_p)) {
                xSemaphoreGiveFromISR(
                    spiLinkDescription_g[i].rxEventSem,
                    &xHigherPriorityTaskWoken);
                break;
            }
        }
    }

    /* Yield to a higher-priority task if one was unblocked */
    portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
}

/**
 * @brief  Scan the link-description table for a free slot.
 *
 * @return  Table index on success, -1 if all slots are occupied.
 */
static int GetLinkDescriptionEntry(void)
{
    int i;
    int freeEntry = -1;

    for (i = 0; i < SES_PORT_MAX_SPI_LINKS; i++) {
        if (spiLinkDescription_g[i].initialized == 0) {
            freeEntry = i;
            break;
        }
    }

    return freeEntry;
}

/**
 * @brief  Stop the IRQ task, disable the interrupt, and clean up resources.
 *
 * Replaces the Windows TerminateThread / FT4222_UnInitialize / FT_Close
 * sequence.
 */
static int SpiClose(int tblIndex)
{
    TickType_t waitTicks =
        pdMS_TO_TICKS(SES_PORT_SPI_WAIT_THREAD_STOP_MS);

    if (spiLinkDescription_g[tblIndex].irqTask == NULL) {
        DBG_INFO("SpiClose: invalid task handle");
        return SES_PORT_INVALID_PARAM;
    }

    /* ── 1. Ask the IRQ task to exit and wake it up ── */
    spiLinkDescription_g[tblIndex].stopTask = 1;
    xSemaphoreGive(spiLinkDescription_g[tblIndex].rxEventSem);

    /*
     * Wait for the task to re-post the semaphore as its exit handshake.
     * If it doesn't respond within the timeout, we give up and return error.
     */
    if (xSemaphoreTake(spiLinkDescription_g[tblIndex].rxEventSem,
                       waitTicks) != pdTRUE) {
        return SES_PORT_ERROR;
    }

    /* ── 2. Disable the GPIO interrupt ── */
    XGpioPs_IntrDisablePin(
        &spiLinkDescription_g[tblIndex].gpioInst,
        SES_PORT_IRQ_GPIO_PIN);

    XScuGic_Disconnect(&XInterruptController, XPAR_PSU_GPIO_0_INTR);

    /* ── 3. Delete the FreeRTOS binary semaphore ── */
    vSemaphoreDelete(spiLinkDescription_g[tblIndex].rxEventSem);
    spiLinkDescription_g[tblIndex].rxEventSem = NULL;

    /* ── 4. Clear the link-description entry ── */
    SES_PORT_WaitSemaphore(spiLinkDescription_g[tblIndex].spiProtectSem,
                           SES_PORT_PROTECTION_TIMEOUT);
    memset(&spiLinkDescription_g[tblIndex], 0,
           sizeof(SES_PORT_spiLinkDescription_t));
    /* NOTE: spiProtectSem is cleared by the memset above; do not signal
     * it after this point.  The SES_PORT_DeleteSemaphore() was called
     * implicitly when the slot was zeroed — if your RTOS heap requires
     * explicit deletion, call it before the memset. */

    return SES_PORT_OK;
}

// End Static Functions *******************************************************

/////////////example_config




#include <stdio.h>

/* FreeRTOS — needed only for vTaskDelay() used in FIRMWARE_UPDATE path */
#include "FreeRTOS.h"
#include "task.h"

/* SES driver headers — unchanged from reference */
#include "SES_PORT_interface.h"
#include "SES_interface_management.h"
#include "SES_configuration.h"
#include "SES_codes.h"

// End Includes ***************************************************************

// Functions ******************************************************************

/**
 * @brief  Initialise the SES stack and configure the ADIN3310 switch ports.
 *
 * Call this once from your FreeRTOS application task (NOT from main() before
 * the scheduler starts) because SES_Init() and SES_AddHwInterface() internally
 * create FreeRTOS objects (semaphores, tasks).
 *
 * Sequence
 * ─────────
 *  1. SES_Init()            — initialise the SES library internals.
 *  2. SES_AddHwInterface()  — register the SPI transport (calls our
 *                             SES_PORT_SPI_Init() which sets up XSpiPs,
 *                             XGpioPs MIO-62, the GIC ISR, and the IRQ task).
 *  3. SES_AddDevice()       — tell the library which MAC address identifies
 *                             this ADIN3310 on the bus.
 *  4. SES_InitializePorts() — push the per-port PHY configuration to the
 *                             switch over SPI.
 *
 * @return SES_PORT_OK on success, negative SES error code on failure.
 */
int32_t sesConfig(void)
{
    int32_t  rv;
    uint8_t  sesPrimaryMac[6] = SES_PRIMARY_MAC;


    /*
     * Initialise to 0, not NULL.
     * interfaceId and deviceId are integers returned by the SES library;
     * assigning NULL (a pointer constant) causes a -Wint-conversion warning
     * with arm-none-eabi-gcc.
     */
    int      interfaceId = 0;
    sesID_t  deviceId    = 0;

    /* ── Port configurations ── */

    /*
     * ADIN6310 — 6-port configuration (kept for completeness; not used when
     * SES_PORT_COUNT == 3 and FIELD_SWITCH == 0).
     */
//    const SES_portInit_t portConfiguration6310[6] = {
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1300, { true, 0, 0, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 0, SES_phyADIN1300, { true, 0, 1, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 0, SES_phyADIN1300, { true, 0, 2, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 0, SES_phyADIN1300, { true, 0, 4, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 0, SES_phyADIN1300, { true, 0, 8, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 0, SES_phyADIN1300, { true, 0, 9, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } }
//    };

    /*
     * ADIN3310 — 3-port configuration.
     * This is the active path for your Zynq build (SES_PORT_COUNT == 3).
     */
    const SES_portInit_t portConfiguration3310[3] = {
        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1300, { true, 0, 0, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } },
        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1300, { true, 0, 1, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } },
        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1300, { true, 0, 2, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } }
    };

//    /* Field Switch Board — 6-port mixed ADIN1100/ADIN1300 configuration */
//    const SES_portInit_t portConfigurationFieldSwitch[6] = {
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1100, { true, 1, 0, SES_phySpeed10,   SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1100, { true, 1, 1, SES_phySpeed10,   SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1300, { true, 1, 6, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1300, { true, 1, 5, SES_phySpeed1000, SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1100, { true, 1, 2, SES_phySpeed10,   SES_phyDuplexModeFull, SES_autoMdix } },
//        { 1, SES_rgmiiMode, { 0, 0, 0 }, 1, SES_phyADIN1100, { true, 1, 3, SES_phySpeed10,   SES_phyDuplexModeFull, SES_autoMdix } }
//    };

    /* ── SES Configuration Over SPI ── */
#ifndef ENABLE_SPI

    /*
     * Register the three SPI transport function pointers.
     * These point to our FreeRTOS/Zynq implementations in
     * SES_PORT_SPI_interface.c — no change needed here.
     */
    SES_driverFunctions_t driverFunctions = {
        .init_p        = SES_PORT_SPI_Init,
        .release_p     = SES_PORT_SPI_Release,
        .sendMessage_p = SES_PORT_SPI_SendMessage
    };

    /*
     * Init parameters for the Zynq PS-SPI port.
     *
     * CHANGED: SES_PORT_ft4222InitParams_t  →  SES_PORT_zynqSpiInitParams_t
     *
     * The FT4222 struct had:
     *   .baseLocationId  — USB location ID, not applicable on Zynq
     *   .spiMode         — single/dual/quad, handled by XSpiPs options
     *
     * Our Zynq struct only needs:
     *   .chipSelect      — which CS line the ADIN3310 is on (0 for single device)
     *
     * SES_PORT_SPI_Init() reads this and passes chipSelect to
     * XSpiPs_SetSlaveSelect() during hardware initialisation.
     */
    SES_PORT_zynqSpiInitParams_t initParameter = {
        .chipSelect = 0    /* ADIN3310 is the only device on CS0 */
    };

    printf("SES Configuration Over SPI (Zynq PS-SPI, MIO-62 IRQ)\n");

    /* Step 1: Initialise SES library internals */
    rv = SES_Init();
    sesGetAppInfo_Example();
    if (rv == SES_PORT_OK) {

        /*
         * Step 2: Register the SPI hardware interface.
         *
         * Internally this calls SES_PORT_SPI_Init() which:
         *   a) Calls XSpiPs_CfgInitialize() — opens the PS-SPI peripheral
         *   b) Calls XGpioPs_CfgInitialize() — opens MIO GPIO
         *   c) Configures MIO pin 62 as input with rising-edge interrupt
         *   d) Connects GpioIsr() to the GIC
         *   e) Creates the FreeRTOS IRQ handler task (TaskSpiIrq)
         *
         * On return, interfaceId is a small integer index (e.g. 0) that
         * identifies this SPI link inside the SES routing layer.
         */
        rv = SES_AddHwInterface(&initParameter, &driverFunctions, &interfaceId);
        if (rv == SES_PORT_OK) {

            /*
             * Step 3: Tell SES the MAC address of the ADIN3310.
             * The library will embed this in the SPI frame headers so the
             * switch can identify the host.
             */
            rv = SES_AddDevice(interfaceId, sesPrimaryMac, &deviceId);
            if (rv == SES_PORT_OK) {

                /*
                 * Step 4: Push port configuration to the ADIN3310 over SPI.
                 * For a 3-port ADIN3310 with FIELD_SWITCH == 0, this sends
                 * portConfiguration3310[] to the switch.
                 */
                if (FIELD_SWITCH) {
//                    rv = SES_InitializePorts(SES_PORT_COUNT,
//                                            portConfigurationFieldSwitch);
                } else if (SES_PORT_COUNT == 6) {
//                    rv = SES_InitializePorts(SES_PORT_COUNT,
//                                            portConfiguration6310);
                } else {
                    rv = SES_InitializePorts(SES_PORT_COUNT,
                                            portConfiguration3310);
                }
            }
        }
    }

#else
    /*
     * SES Configuration Over Ethernet — retained for reference only.
     * This path is NOT used on Zynq (we use SPI).
     * Compile with -DENABLE_SPI to always take the SPI path above.
     */
    uint8_t hostMac[6] = HOST_MAC;

    SES_driverFunctions_t driverFunctions = {
        .init_p          = SES_PORT_ETH_Init,
        .release_p       = SES_PORT_ETH_Release,
        .sendMessage_p   = SES_PORT_ETH_SendMessage,
        .updateFilter_p  = SES_PORT_ETH_UpdateFilter
    };

    printf("SES Configuration Over Ethernet\n");

    rv = SES_Init();
    if (rv == SES_PORT_OK) {
        rv = SES_AddHwInterface(hostMac, &driverFunctions, &interfaceId);
        if (rv == SES_PORT_OK) {
            rv = SES_AddDevice(interfaceId, sesPrimaryMac, &deviceId);
            if (rv == SES_PORT_OK) {
                if (FIELD_SWITCH) {
                    rv = SES_InitializePorts(6, portConfigurationFieldSwitch);
                } else if (SES_PORT_COUNT == 6) {
                    rv = SES_InitializePorts(SES_PORT_COUNT, portConfiguration6310);
                } else {
                    rv = SES_InitializePorts(SES_PORT_COUNT, portConfiguration3310);
                }
            }
        }
    }
#endif

    return rv;
}

/* ── Helper: print firmware version info ── */
void sesGetAppInfo_Example(void)
{
    SES_appInfo_t appInfo;

    printf("---------------------FIRMWARE DETAILS----------------------\n");
    SES_GetFirmwareInfo(&appInfo, sizeof(appInfo));
    printf("appInfoVersion :: %d\n",  appInfo.appInfoVersion);
    printf("buildNumber    :: %d\n",  appInfo.buildNumber);
    printf("name           :: %s\n",  appInfo.name);
    printf("part Number    :: %s\n",  appInfo.partNum);
    printf("Version        :: %s\n",  appInfo.version);
    printf("-----------------------------------------------\n\n");
}

/**
 * @brief  Run whichever protocol examples are selected via compile-time flags.
 *
 * The interactive TIME_SYNC loop uses scanf() which works on the Vitis UART
 * console.  If your application has no stdin, remove or guard that block.
 *
 * CHANGED: Sleep(5000) → vTaskDelay(pdMS_TO_TICKS(5000))
 *   Sleep() is a Windows API (milliseconds).
 *   vTaskDelay() is the FreeRTOS equivalent — it yields the current task for
 *   the given number of ticks, letting other tasks run during the wait.
 *   pdMS_TO_TICKS() converts 5000 ms → the correct tick count regardless of
 *   configTICK_RATE_HZ.
 */
void sesProtocolInitialization_Example(void)
{
//    int input;

//    if (DEFAULT_SWITCH) {
//        printf("Initializing the switch with default configurations !!\n");
//        sesLldpInit_Example();
//        sesSingleASPtpInstance_Example();
//        sesMstpStackStart_Example();
//    }
//    else if (HSR_PRP) {
//        sesHsrPrp_Example();
//    }
//    else {
//        if (TIME_SYNC)          { sesTimeSync_Example(); }
//        if (SCHEDULED_TRAFFIC)  { sesScheduledTrafficGuardBand_Example(); }
//        if (FRAME_PREEMPTION)   { sesSetPreemptionConfigurationStructure_Example(); }
//        if (SENDLIST)           { sesSendlist_Example(); }
//        if (FRER)               { sesFrer_Example(); }
//        if (PSFP)               { sesPsfp_Example(); }
//        if (MRP)                { sesMrp_Example(); }
//        if (MSTP)               { sesMultipleMsti_Example(); }
//    }
//
//    if (EVENT)           { sesEvent_Example(); }
//    if (LLDP_INIT)       { sesLldpInit_Example(); }
//
//    if (FIRMWARE_UPDATE) {
//        sesFirmwareUpdate_Example();
//        /*
//         * CHANGED: Sleep(5000) → vTaskDelay(pdMS_TO_TICKS(5000))
//         *
//         * Wait 5 seconds for the firmware update to complete.
//         * vTaskDelay() blocks ONLY this task; the FreeRTOS scheduler
//         * continues running other tasks (IRQ handler, idle, etc.) during
//         * the wait.  Sleep() on Windows would have blocked the whole thread.
//         */
//        vTaskDelay(pdMS_TO_TICKS(5000));
//    }
//
//    if (IGMP_SNOOPING)   { sesIgmp_Example(); }
//    if (VLAN_CONFIG)     { sesVlan_Example(); }
//    if (SWITCH_EXAMPLE)  { sesSwitch_Example(); }
//    if (LAYER_2)         { seslayer2_Example(); }
//    if (UPDATE_SOURCE_MAC) { sesUpdateMACAddress_Example(); }
//
//    /*
//     * Interactive PTP parameter read loop.
//     * Runs on the Vitis UART console (stdin/stdout routed to UART0 by BSP).
//     * The while(1) here is intentional — the user types 9 to exit.
//     */
//    if (TIME_SYNC) {
//        while (1) {
//            printf("\n");
//            printf("*-------- Time Sync Read Parameters --------\n");
//            printf("1: Read Port Specific Parameters\n");
//            printf("2: Read CMLDS Specific Parameters\n");
//            printf("9: Exit\n");
//            scanf("%d", &input);
//            printf("Option Entered :: %d\n", input);
//
//            if (input == 9) {
//                break;
//            } else {
//                sesGetPtpParameters_Example(input);
//            }
//        }
//    }
}

// End Functions **************************************************************


//////memory and semaphore


// Includes *******************************************************************

#include "FreeRTOS.h"       /* pvPortMalloc / vPortFree                       */
#include "SES_port_api.h"

// End Includes ***************************************************************

// Macros, typedefs, enums ****************************************************

/*
 * The Windows reference implementation rounds every allocation up to 98 bytes
 * to mimic the fixed-block FIFO mempool behaviour of the original RTOS port.
 * Keep the same floor so that buffer-size assumptions in the SES driver hold.
 */
#define SES_PORT_MIN_BLK_SIZE   (98U)

// End Macros, typedefs, enums ************************************************

// Functions ******************************************************************

/**
 * @brief  Allocate a buffer of at least @p size bytes.
 *
 * Uses FreeRTOS heap (pvPortMalloc) so the allocation is thread-safe and
 * participates in the same heap-4/heap-5 pool as the rest of the application.
 *
 * @param[out] buf_pp  Receives the address of the allocated buffer.
 * @param[in]  size    Minimum number of bytes required.
 *
 * @retval SES_PORT_OK       Allocation succeeded; *buf_pp is valid.
 * @retval SES_PORT_BUF_ERR  buf_pp is NULL, or heap exhausted.
 */
int32_t SES_PORT_Malloc(void **buf_pp, int size)
{
    if (buf_pp == NULL) {
        return SES_PORT_BUF_ERR;
    }

    /* Mirror the reference: enforce a minimum block size */
    if (size < (int)SES_PORT_MIN_BLK_SIZE) {
        size = (int)SES_PORT_MIN_BLK_SIZE;
    }
    
    
    
    
    
#include "FreeRTOS.h"
#include "semphr.h"         /* SemaphoreHandle_t, xSemaphoreCreateCounting … */
#include "SES_port_api.h"

// End Includes ***************************************************************

// Macros, typedefs, enums ****************************************************

/*
 * Helper: convert the opaque (int*) handle used by the SES API back into
 * a FreeRTOS SemaphoreHandle_t.  Both are pointer-sized on Cortex-A53.
 */
#define TO_SEM_HANDLE(p)    ((SemaphoreHandle_t)(p))

// End Macros, typedefs, enums ************************************************

// Functions ******************************************************************

/**
 * @brief  Create a counting semaphore.
 *
 * @param[in] initCount  Initial semaphore count (tokens available immediately).
 * @param[in] maxCount   Maximum semaphore count.
 *
 * @return  Opaque handle cast to (int*) on success, NULL on failure.
 *
 * @note  maxCount must be >= initCount and >= 1, otherwise
 *        xSemaphoreCreateCounting() returns NULL.
 */
void* SES_PORT_CreateSemaphore(int initCount, int maxCount)
{
    SemaphoreHandle_t sem;

    sem = xSemaphoreCreateCounting((UBaseType_t)maxCount,
                                   (UBaseType_t)initCount);
    if (sem == NULL) {
        return NULL;
    }

    /*
     * Cast to (int*) to match the SES API signature.
     * The actual value stored is a FreeRTOS queue handle (pointer).
     */
    return (int*)sem;
}

/**
 * @brief  Wait (take) a semaphore, blocking for up to @p timeout ms.
 *
 * @param[in] semaphore_p  Handle returned by SES_PORT_CreateSemaphore().
 * @param[in] timeout      Maximum wait time in milliseconds.
 *                         Pass portMAX_DELAY_MS (0xFFFFFFFF) to wait forever.
 *
 * @retval SES_PORT_OK             Semaphore taken successfully.
 * @retval SES_PORT_TIMEOUT        Timed out before the semaphore was available.
 * @retval SES_PORT_INVALID_PARAM  semaphore_p is NULL.
 * @retval SES_PORT_ERROR          Unexpected FreeRTOS error.
 */
int32_t SES_PORT_WaitSemaphore(int* semaphore_p, int timeout)
{
    BaseType_t result;
    TickType_t ticks;

    if (semaphore_p == NULL) {
        return SES_PORT_INVALID_PARAM;
    }

    /*
     * Convert milliseconds → FreeRTOS ticks.
     * A timeout of portMAX_DELAY (0xFFFFFFFF ms) is treated as "wait forever"
     * so we propagate it as portMAX_DELAY ticks without overflow.
     */
    if ((uint32_t)timeout == 0xFFFFFFFFU) {
        ticks = portMAX_DELAY;
    } else {
        ticks = pdMS_TO_TICKS((uint32_t)timeout);
    }

    result = xSemaphoreTake(TO_SEM_HANDLE(semaphore_p), ticks);

    if (result == pdTRUE) {
        return SES_PORT_OK;
    }

    /*
     * FreeRTOS returns pdFALSE for both timeout and other failures;
     * in normal usage this is always a timeout (the semaphore was not
     * signalled within the allotted time).
     */
    return SES_PORT_TIMEOUT;
}

/**
 * @brief  Signal (give) a semaphore.
 *
 * @param[in] semaphore_p  Handle returned by SES_PORT_CreateSemaphore().
 *
 * @retval  1 (non-zero)          Semaphore signalled successfully.
 * @retval  0                     xSemaphoreGive() failed (count at maximum).
 * @retval  SES_PORT_INVALID_PARAM  semaphore_p is NULL.
 *
 * @note  Must NOT be called from an ISR.  If you need to signal from an ISR,
 *        replace xSemaphoreGive() with xSemaphoreGiveFromISR() and handle
 *        the higher-priority task wakeup accordingly.
 */
int32_t SES_PORT_SignalSemaphore(int* semaphore_p)
{
    BaseType_t result;

    if (semaphore_p == NULL) {
        return SES_PORT_INVALID_PARAM;
    }

    result = xSemaphoreGive(TO_SEM_HANDLE(semaphore_p));

    /*
     * Mirror the Windows port: return non-zero on success, zero on failure.
     * (The SES driver checks the return value as a boolean.)
     */
    return (result == pdTRUE) ? 1 : 0;
}

/**
 * @brief  Delete a semaphore and free its resources.
 *
 * @param[in] semaphore_p  Handle returned by SES_PORT_CreateSemaphore().
 *
 * @retval  1 (non-zero)          Semaphore deleted successfully.
 * @retval  SES_PORT_INVALID_PARAM  semaphore_p is NULL.
 *
 * @note  After this call the handle is invalid; do not use it again.
 *        Ensure no task is blocked on the semaphore before deleting it.
 */
int32_t SES_PORT_DeleteSemaphore(int* semaphore_p)
{
    if (semaphore_p == NULL) {
        return SES_PORT_INVALID_PARAM;
    }

    vSemaphoreDelete(TO_SEM_HANDLE(semaphore_p));

    /*
     * vSemaphoreDelete() is void — it always succeeds when given a valid
     * handle.  Return non-zero to indicate success, consistent with the
     * Windows reference implementation.
     */
    return 1;
}

// End Functions **************************************************************

ADIN6310 over SPI: FRER Stream Identification Failing (No R-TAGs, Listener Stats Zero)

prahadeeshDP — Sat, 30 May 2026 06:04:21 GMT

Hello!🙌

I am trying to implement IEEE 802.1CB (FRER) using two ADIN6310 evaluation kits connected to Texas Instruments AM62P MPUs over SPI in Linux.

Standard switching and ping work perfectly with my general configuration, but I am struggling to get the FRER Talker and Listener proxies to actually encapsulate/decapsulate the traffic. Normal TCP data is successfully received, but the FRER mechanisms appear to be bypassed.

Hardware & Topology Setup:

Host A (Talker Node): TI AM62P MPU connected via SPI to ADIN6310 Eval Kit 1.
Host B (Listener Node): TI AM62P MPU connected via SPI to ADIN6310 Eval Kit 2.
Topology:
- Host 1 (AM62p - 1) Eth0 <---> [Port 1] Talker ADIN6310 -1
- Talker ADIN6310 -1 [Port 4] <---> [Port 4] Listener ADIN6310 - 2 (Path A)
- Talker ADIN6310 -1 [Port 5] <---> [Port 5] Listener ADIN6310 - 2 (Path B)
- Listener ADIN6310 - 2 [Port 1] <---> Host 2 (AM62p - 2) Eth0

Software & Configuration Context:

VLAN: VLAN 100 allowed on all ports (SES_SetVlanMode(100, 0xFFF)).
MSTP is disabled. Using Unicast/Multicast miss return for basic loop protection between ports 4 and 5.
I am utilizing the sample code logic provided in the driver user guide for Talker/Listener stream configuration but I changed the redundant ports.
Config the VLAN 100 in both AM62p

The Talker Script VLAN

#!/bin/sh

echo "Configuring FRER Talker Network Interfaces..."

# 1. Bring up the physical interface
ip link set eth0 up

# 2. Create a VLAN 100 interface and assign an IP
ip link add link eth0 name eth0.100 type vlan id 100
ip addr add 192.168.100.1/24 dev eth0.100
ip link set eth0.100 up

# 3. Force the ARP table to map the Listener's IP to the hardcoded FRER Dest MAC
arp -s 192.168.100.2 C0:D6:0A:F9:6A:D8

echo "Talker setup complete! Ping traffic to 192.168.100.2 will now trigger FRER."

The Listener Script VLAN

#!/bin/sh

echo "Configuring FRER Listener Network Interfaces..."

# 1. Bring up the physical interface
ip link set eth0 up

# 2. Create a VLAN 100 interface and assign an IP
ip link add link eth0 name eth0.100 type vlan id 100
ip addr add 192.168.100.2/24 dev eth0.100
ip link set eth0.100 up

echo "Listener setup complete! Ready to receive FRER traffic on 192.168.100.2."

The Issue: To test the FRER redundancy, I am running a simple unidirectional TCP client/server counter program from Host A to Host B. by VLAN's IP 192.168.100.2

Data Arrives: The server on Host B successfully receives the counter data.
No FRER Tags: I connected talker end to AM62P's to 2 ethernet eth0 and etn1 for capture RTAG, I perform a packet capture (pcap format) on the AM62P monitoring the FRER ports (Ports 4 & 5), there is no FRER ID / R-TAG sequence number injected into the packets.
Zero Statistics: Polling SES_FrerGetSequenceRecoveryStatistics() continuously returns 0 for rxPassedPkts, rxDiscardedPkts, etc., despite data flowing.

Stream Identification Configuration code:

/*
 * Copyright (c) 2024 - 2026 Analog Devices, Inc. All Rights Reserved.
 */

#include <stdlib.h>
#include <stdio.h>
#include <getopt.h>
#include <string.h>
#include <unistd.h>
#include <signal.h>
#include <inttypes.h>
#include <sys/types.h>
#include <sys/wait.h>

#include "SES_PORT_interface.h"
#include "SES_interface_management.h"
#include "SES_codes.h"
#include "SES_switch.h"
#include "SES_port_api.h"
#include "EX_ses_example_app.h"
#include "EX_util.h"
#include "SES_app_debug.h"
#include "SES_frer.h" // Essential for FRER configurations

#define PORT_COUNT 6
#define SPI_SPEED 16000000

// Port Map Definitions
#define SES_PORT_0 0
#define SES_PORT_1 1
#define SES_PORT_2 2
#define SES_PORT_3 3
#define SES_PORTMAP_PORT_0 1
#define SES_PORTMAP_PORT_1 2
#define SES_PORTMAP_PORT_2 4
#define SES_PORTMAP_PORT_3 8
#define SES_PORTMAP_PORT_4 16
#define SES_PORTMAP_PORT_5 32

// Global Variables
uint8_t AppRunningStatus = 1;
struct sigaction sa;

// Function Prototypes
static bool EX_IsSpiModeValid(int spiMode);
static int EX_HardcodeBoardSettings(uint8_t * primaryMac, uint8_t * portCount, SES_portInit_t * initializePorts_p);
void handle_sigint(int sig);

// FRER & Loop Protection Prototypes
int32_t EX_ConfigureLoopPreventionMissReturn(void);
int32_t configure_adin6310_talker(int32_t * frerTableIndex);
int32_t configure_adin6310_listener(int32_t * listenerFrerTableIndex);
int32_t sesGetFrerListenerStatistics(int32_t listenerFrerTableIndex);

int main(int argc, char ** argv)
{
    int opt;
    int interfaceId = -1;
    int rv = SES_OK;
    char * interface_p = NULL;
    printf("Version :- FRER(Embedded AM62p)\n");
    
#if SPIDEV
    const char * readyPin_p = NULL;
#endif

    uint8_t primaryMac[6] = {0};
    uint8_t hostMac[6] = {0};
    uint8_t portCount;
    SES_portInit_t initializePorts_p[SES_MAX_PORTS] = {0};
    sesID_t deviceId = -1;
    SES_driverFunctions_t driverFunctions = {0};

#if SPIDEV
    SES_PORT_SpidevInitParams_t spiInitParams = {0};
    while ((opt = getopt(argc, argv, "p:g:s:lh")) != -1)
#else
    SES_PORT_ft4222InitParams_t spiInitParams = {{0}, 0, SES_PORT_SPI_notUsed};
    while ((opt = getopt(argc, argv, "p:s:lh")) != -1)
#endif
    {
        switch (opt)
        {
        case 'p':
            interface_p = optarg;
            break;
#if SPIDEV
        case 'g':
            readyPin_p = optarg;
            break;
#endif
        case 's':
            spiInitParams.spiMode = strtol(optarg, NULL, 10);
            break;
        case 'h':
        default:
            printf("Usage: %s -p <interface> [-s <mode>]\n", argv[0]);
            exit(EXIT_FAILURE);
        }
    }

    // 1. Initialize Board Settings
    rv = EX_HardcodeBoardSettings(primaryMac, & portCount, initializePorts_p);
    if (rv != SES_OK)
        exit(EXIT_FAILURE);

    // 2. Initialize SES Library
    if (SES_Init() != SES_OK)
        return -1;

    // 3. YOUR SPI/Ethernet Selection Logic
    if (spiInitParams.spiMode == SES_PORT_SPI_notUsed)
    {
        if (EX_StringToMacAddress(interface_p, hostMac, ":") != SES_OK)
            exit(EXIT_FAILURE);

        driverFunctions.init_p = SES_PORT_ETH_Init;
        driverFunctions.release_p = SES_PORT_ETH_Release;
        driverFunctions.sendMessage_p = SES_PORT_ETH_SendMessage;
        driverFunctions.updateFilter_p = SES_PORT_ETH_UpdateFilter;
        rv = SES_AddHwInterface(hostMac, & driverFunctions, & interfaceId);
    } else
    {
#if SPIDEV
        if (interface_p)
            spiInitParams.spiDevice = interface_p;
        if (readyPin_p)
            spiInitParams.gpioPin = readyPin_p;
        spiInitParams.speed = SPI_SPEED;
#else
        if (interface_p)
            spiInitParams.deviceIndex = strtol(interface_p, NULL, 10);
#endif
        driverFunctions.init_p = SES_PORT_SPI_Init;
        driverFunctions.release_p = SES_PORT_SPI_Release;
        driverFunctions.sendMessage_p = SES_PORT_SPI_SendMessage;
        rv = SES_AddHwInterface( & spiInitParams, & driverFunctions, & interfaceId);
    }

    if (rv != SES_OK)
        return rv;

    // 4. Add Device and Initialize ALL Ports
    rv = SES_AddDevice((uint32_t) interfaceId, primaryMac, & deviceId);
    if (rv == SES_OK)
    {
        rv = SES_InitializePorts(portCount, initializePorts_p);
        if (rv == SES_OK) {
            EX_ConfigureLoopPreventionMissReturn();
        }
    }

    // Print the Firmware Version
    sesGetAppInfo();

    // 6. Apply FRER Configuration
    int32_t talkerFrerTableIndex = -1;
    int32_t listenerFrerTableIndex = -1;

    switch (Frer_Config_opt) {
    case 1: // Talker
        configure_adin6310_talker( & talkerFrerTableIndex);
        printf("SES Application Running: FRER Talker Proxy\n");
        break;
    case 2: // Listener
        configure_adin6310_listener( & listenerFrerTableIndex);
        printf("SES Application Running: FRER Listener Proxy\n");
        break;
    default:
        printf("No FRER Config\n");
    }

    // Setup ISR and Loop
    sa.sa_handler = & handle_sigint;
    sigaction(SIGINT, & sa, NULL);
    printf("Setup Finish\n");

    while (AppRunningStatus)
    {
        switch (Frer_Config_opt) {
        case 1: // Talker
            //printf(".\n"); // Keepalive marker for Talker
            break;
        case 2: // Listener
            sesGetStatisticsPortStatistics(6);
            sesGetFrerListenerStatistics(listenerFrerTableIndex);
            break;
        default: // No Frer config
            printf("No FRER Config");
        }
        sleep(2); // Wait 2 seconds before repolling stats
    }

    SES_RemoveHwInterface(interfaceId);
    return 0;
}

// ---------------------------------------------------------------------
// Loop Protection (Approach 2 - Miss Return)
// ---------------------------------------------------------------------
int32_t EX_ConfigureLoopPreventionMissReturn(void)
{
    int32_t rv = 0;
    uint8_t portMap;
    bool cutThrough;
    uint8_t lookupDone;
    uint8_t txFilter;
    bool txFilterValid;
    uint8_t rxFilter;
    bool rxFilterValid;

    rv = SES_GetUnicastMissReturn(SES_macPort4, & portMap, & cutThrough, & lookupDone, & txFilter, & txFilterValid, & rxFilter, & rxFilterValid);
    if (rv == SES_PORT_OK) {
        portMap = portMap & ~(1 << 5); // 1 << 5 represents Port 5
        SES_SetUnicastMissReturn(SES_macPort4, portMap, cutThrough, lookupDone, txFilter, txFilterValid, rxFilter, rxFilterValid);
    }
    rv = SES_GetMulticastMissReturn(SES_macPort4, & portMap, & cutThrough, & lookupDone, & txFilter, & txFilterValid, & rxFilter, & rxFilterValid);
    if (rv == SES_PORT_OK) {
        portMap = portMap & ~(1 << 5);
        SES_SetMulticastMissReturn(SES_macPort4, portMap, cutThrough, lookupDone, txFilter, txFilterValid, rxFilter, rxFilterValid);
    }

    rv = SES_GetUnicastMissReturn(SES_macPort5, & portMap, & cutThrough, & lookupDone, & txFilter, & txFilterValid, & rxFilter, & rxFilterValid);
    if (rv == SES_PORT_OK) {
        portMap = portMap & ~(1 << 4); // 1 << 4 represents Port 4
        SES_SetUnicastMissReturn(SES_macPort5, portMap, cutThrough, lookupDone, txFilter, txFilterValid, rxFilter, rxFilterValid);
    }
    rv = SES_GetMulticastMissReturn(SES_macPort5, & portMap, & cutThrough, & lookupDone, & txFilter, & txFilterValid, & rxFilter, & rxFilterValid);
    if (rv == SES_PORT_OK) {
        portMap = portMap & ~(1 << 4);
        SES_SetMulticastMissReturn(SES_macPort5, portMap, cutThrough, lookupDone, txFilter, txFilterValid, rxFilter, rxFilterValid);
    }

    printf("Loop Protection (Miss Return Approach) Applied between Ports 4 & 5.\n");
    return SES_PORT_OK;
}

// ---------------------------------------------------------------------
// FRER Talker Configuration
// ---------------------------------------------------------------------
int32_t configure_adin6310_talker(int32_t * frerTableIndex)
{
    int32_t rv = 0;
    uint8_t destinationMAC[6] = {0xC0, 0xD6, 0x0A, 0xF9, 0x6A, 0xD8};
    TSN_ieee802Dot1cbFrer_t frerParameters;
    TSN_ieee802Dot1cbStream_t streamParameters;
    TSN_ieee802Dot1cbMaskAndMatch_t maskAndMatchParameters;

    memset( & frerParameters, 0, sizeof(TSN_ieee802Dot1cbFrer_t));
    memset( & streamParameters, 0, sizeof(TSN_ieee802Dot1cbStream_t));
    memset( & maskAndMatchParameters, 0, sizeof(TSN_ieee802Dot1cbMaskAndMatch_t));

    rv = SES_SetVlanMode(100, 0xFFF); // Allow VLAN 100 on all switch ports
    if (rv < SES_PORT_OK) printf("SES_SetVlanMode Error :: %d\n", rv);

    // Stream table Parameters
    streamParameters.TSN_streamIdentity.identificationType = TSN_nullStream;
    for (int i = 0; i < 6; i++) {
        streamParameters.TSN_streamIdentity.TSN_parameters.TSN_nullStreamIdentification.destinationMac[i] = destinationMAC[i];
    }
    streamParameters.TSN_streamIdentity.TSN_parameters.TSN_nullStreamIdentification.vlan = 100;

    streamParameters.portMap = SES_PORTMAP_PORT_4 | SES_PORTMAP_PORT_5;
    streamParameters.TSN_HardwareTableIndices.dynTblIdx[0] = -1;
    streamParameters.TSN_HardwareTableIndices.dynTblIdx[1] = -1;
    streamParameters.TSN_HardwareTableIndices.exTblruleId = -1;
    streamParameters.useStreamtable = false;

    frerParameters.TSN_sequenceGeneration.reset = false;
    frerParameters.TSN_sequenceRecovery.individualRecovery = false;

    frerParameters.TSN_streamSplit.port = SES_PORT_1;
    frerParameters.TSN_HardwareTableIndices.individualRecoveryTblIdx = -1;
    frerParameters.TSN_HardwareTableIndices.sequenceGenerationTblIdx = -1;
    frerParameters.TSN_HardwareTableIndices.sequenceRecoveryTblIdx = -1;
    frerParameters.TSN_HardwareTableIndices.txTransformTblIdx = -1;

    rv = SES_FrerConfigureTalkerProxyForStream( & frerParameters, & streamParameters, & maskAndMatchParameters);
    if (rv == SES_PORT_OK) {
        * frerTableIndex = frerParameters.TSN_HardwareTableIndices.sequenceGenerationTblIdx;
    }
    return rv;
}

// ---------------------------------------------------------------------
// FRER Listener Configuration & Statistics
// ---------------------------------------------------------------------
int32_t configure_adin6310_listener(int32_t * listenerFrerTableIndex)
{
    int32_t rv = 0;
    uint8_t destinationMAC[6] = {0xC0, 0xD6, 0x0A, 0xF9, 0x6A, 0xD8};
    TSN_ieee802Dot1cbFrer_t frerParameters;
    TSN_ieee802Dot1cbStream_t streamParameters;
    TSN_ieee802Dot1cbMaskAndMatch_t maskAndMatchParameters;

    memset( & frerParameters, 0, sizeof(TSN_ieee802Dot1cbFrer_t));
    memset( & streamParameters, 0, sizeof(TSN_ieee802Dot1cbStream_t));
    memset( & maskAndMatchParameters, 0, sizeof(TSN_ieee802Dot1cbMaskAndMatch_t));

    rv = SES_SetVlanMode(100, 0xFFF);
    streamParameters.TSN_streamIdentity.identificationType = TSN_nullStream;
    for (int i = 0; i < 6; i++) {
        streamParameters.TSN_streamIdentity.TSN_parameters.TSN_nullStreamIdentification.destinationMac[i] = destinationMAC[i];
    }
    streamParameters.TSN_streamIdentity.TSN_parameters.TSN_nullStreamIdentification.vlan = 100;

    // Output reconstructed data strictly out of Port 1
    streamParameters.portMap = SES_PORTMAP_PORT_1;
    streamParameters.TSN_HardwareTableIndices.dynTblIdx[0] = -1;
    streamParameters.TSN_HardwareTableIndices.dynTblIdx[1] = -1;
    streamParameters.TSN_HardwareTableIndices.exTblruleId = -1;
    streamParameters.useStreamtable = false;

    frerParameters.TSN_sequenceRecovery.algorithm = TSN_vector; // Or TSN_match
    frerParameters.TSN_sequenceRecovery.historyLength = 5;
    frerParameters.TSN_sequenceRecovery.resetTimeout = 0xffff;
    frerParameters.TSN_sequenceRecovery.takeNoSequence = false;
    frerParameters.TSN_sequenceRecovery.individualRecovery = false;

    frerParameters.TSN_HardwareTableIndices.individualRecoveryTblIdx = -1;
    frerParameters.TSN_HardwareTableIndices.sequenceGenerationTblIdx = -1;
    frerParameters.TSN_HardwareTableIndices.sequenceRecoveryTblIdx = -1;
    frerParameters.TSN_HardwareTableIndices.txTransformTblIdx = -1;

    rv = SES_FrerConfigureListenerProxyForStream( & frerParameters, & streamParameters, & maskAndMatchParameters);
    if (rv == SES_PORT_OK) {
        * listenerFrerTableIndex = frerParameters.TSN_HardwareTableIndices.sequenceRecoveryTblIdx;
    }
    return rv;
}

int32_t sesGetFrerListenerStatistics(int32_t listenerFrerTableIndex)
{
    if (listenerFrerTableIndex == -1) return SES_OK;
    int rv = SES_OK;
    TSN_ieee802Dot1cbFrer_t monitorParams;

    memset( & monitorParams, 0, sizeof(TSN_ieee802Dot1cbFrer_t));
    monitorParams.TSN_HardwareTableIndices.sequenceRecoveryTblIdx = listenerFrerTableIndex;
    monitorParams.TSN_sequenceRecovery.port = 0;

    rv = SES_FrerGetSequenceRecoveryStatistics( & monitorParams);
    if (rv == SES_PORT_OK) {
        printf("\n--- FRER Listener Stats ---\n");
        printf(" Passed Packets (Valid)   :: %llu\n", monitorParams.TSN_perPortPerStreamCounters.rxPassedPkts);
        printf(" Discarded Packets (Dups) :: %llu\n", monitorParams.TSN_perPortPerStreamCounters.rxDiscardedPkts);
        printf(" Lost Packets             :: %llu\n", monitorParams.TSN_perPortPerStreamCounters.rxLostPkts);
        printf(" Out Of Order Packets     :: %llu\n", monitorParams.TSN_perPortPerStreamCounters.rxOutOfOrderPkts);
        printf(" Rogue Packets            :: %llu\n", monitorParams.TSN_perPortPerStreamCounters.rxRoguePkts);
    } else {
        printf("Failed to read FRER stats: %d\n", rv);
    }
    return rv;
}

// ---------------------------------------------------------------------
// Basic Environment Setup
// ---------------------------------------------------------------------
static int EX_HardcodeBoardSettings(uint8_t * primaryMac, uint8_t * portCount, SES_portInit_t * initializePorts_p)
{
    uint8_t mac_addr[6] = {0x7A, 0xC6, 0xBB, 0x11, 0x11, 0x11};
    memcpy(primaryMac, mac_addr, 6);
    * portCount = PORT_COUNT;

    for (int i = 0; i < * portCount; i++)
    {
        initializePorts_p[i].enablePort = 1;
        initializePorts_p[i].mii = SES_rgmiiMode;
        initializePorts_p[i].phyConfig.autoNegEnable = true;
        initializePorts_p[i].phyConfig.speed = SES_phySpeed1000;
        initializePorts_p[i].phyConfig.duplexMode = SES_phyDuplexModeFull;
        initializePorts_p[i].phyConfig.crossover = SES_autoMdi;
        initializePorts_p[i].miiClkDelays.enableRxDelay = SES_DISABLE_DELAY;
        initializePorts_p[i].miiClkDelays.enableTxDelay = SES_DISABLE_DELAY;
        initializePorts_p[i].miiClkDelays.clkSelection = SES_CLK_INTERNAL;
        initializePorts_p[i].phyConfig.phyPullupCtrl = SES_PHY_PULLUP_INTERNAL;
        
        uint8_t addrs[] = {0, 1, 2, 4, 8, 9};
        initializePorts_p[i].phyConfig.phyAddr = addrs[i];

        if (i == 0)
        {
            initializePorts_p[i].phyType = SES_phyUnmanaged;
            initializePorts_p[i].linkStatusPolarity = SES_LINK_ACTIVE_LOW;
        } else
        {
            initializePorts_p[i].phyType = SES_phyADIN1300;
        }
    }
    return SES_OK;
}

static bool EX_IsSpiModeValid(int spiMode)
{
    return (spiMode >= 0 && spiMode <= 4);
}

void handle_sigint(int sig)
{
    (void) sig; // Acknowledge parameter to stop compiler warning
    AppRunningStatus = 0;
}

From the below function I configured based on what given in driver guide

int32_t EX_ConfigureLoopPreventionMissReturn(void);
int32_t configure_adin6310_talker(int32_t * frerTableIndex);
int32_t configure_adin6310_listener(int32_t * listenerFrerTableIndex);
int32_t sesGetFrerListenerStatistics(int32_t listenerFrerTableIndex);

I need to know is that anything I missed or I did some thing wrong.

Thank you.

Regarding the latency of ADIN6310/ADIN3310

UBOTI — Fri, 24 Apr 2026 09:33:45 GMT

I'd like to confirm some details regarding the latency of the ADIN6310/ADIN3310.
Q1: Is it acceptable to use the CUT-THROUGH value for SWITCH LATENCY regardless of whether HRS is used or not?
Q2: The datasheet doesn't mention RGMII; is it okay to treat SGMII PHY LATENCY as an approximation?
Q3: Please provide any other documentation regarding the device's latency.

ADIN 3310 SPI host interface - MISO not responsive during bring-up

JoanGCL — Mon, 13 Apr 2026 17:15:47 GMT

We are currently evaluating the ADIN3310 using the EVAL‑ADIN3310 development board. Our intended workflow is to perform an initial configuration over SPI, and then hand over control to Ethernet Port 0.

We have built and integrated the ADIN33x0 TSN driver library, and configured the switch to use single‑SPI as the host interface. During bring‑up, the initialization fails with a timeout in SES_AddDevice(), and we observe no activity on the MISO line. Additionally, TIMER0 remains low.

On the bus side, CS, SCLK, and MOSI appear correct on the scope. The driver sends a 32‑bit SPI transaction (repeated twice), but no response is received from the ADIN3310. At this point, we would expect valid data to be driven on MISO for device enumeration.

What we checked so far:

- The device has valid firmware: We can successfully connect to the ADIN3310 by configuring Ethernet Port 0 as the host interface.
- Bootstrapping pins are correctly set at reset: CS, TIMER0, TIMER1 = HIGH, TIMER2, TIMER3 = LOW.
- Supply voltages: VDD and the SPI I/O voltage are both at 3.3 V.
- SPI configuration: Clock reduced to 100 kHz and all four SPI modes tested.

Given the timeout in SES_AddDevice(), we suspect the ADIN3310 is not responding as expected to the initial SPI discovery/handshake sequence.

During SES_AddDevice(), is the ADIN3310 expected to drive MISO and return a valid response in single‑SPI mode, or is a prior configuration/state (e.g., TIMER0 assertion, SPI_SIO configuration, or alternate frame format) required before MISO becomes active?

Any guidance on additional checks or common SPI bring‑up pitfalls around SES_AddDevice() would be greatly appreciated.

#adin3310 SES AddDevice error -1

Kiranmaye — Fri, 10 Apr 2026 08:04:56 GMT

Hello,

I am trying to configure the ADIN3310 Ethernet switch using the SPI interface. I built the **ses-example-app** through cross-compilation on my Ubuntu host system, targeting a custom board based on the Kria K26 SoM running PetaLinux.

After successfully building the application, I transferred the executable to the target board and attempted to run it with the following command:

sudo LD_LIBRARY_PATH=/home/petalinux/adin3310/deploy_libs ./ses-example-app -f example-eval-6310.xml -g /dev/gpiochip0:5 -p /dev/spidev3.0 -m sysrepo-glue-srv/modules/ -s 1 -i production -l

The application starts but fails during initialization with the following output:

Interface Information:
-- /dev/spidev3.0, /dev/spidev1.0

Board settings file is located at example-eval-6310.xml
Yang modules folder sysrepo-glue-srv/modules/
libyang[0]: Value "00" was not found in the dictionary.
libyang[1]: String "00" not freed from the dictionary, refcount 1
Device MAC: 00:E0:22:12:34:56
Init with device on: /dev/spidev3.0 ready_pin:/dev/gpiochip0:5 speed:16000000
SES AddDevice error -1

The failure occurs during the device initialization step (SES AddDevice error -1). SPI pin strapping is configured correctly, but no pulses are observed on Timer0. A dummy MAC address is used in the XML file. I am not sure whether this is related to SPI communication, GPIO configuration, device tree settings, or the libyang/sysrepo setup.

Could you please help identify what might be causing this issue and what I should check or modify to resolve it?

Thank you.

ADIN6310 custom hardware verification

BW866 — Tue, 31 Mar 2026 19:47:05 GMT

Hello,

I have been working on verifying some custom hardware with the ADIN6310. I am having some troubles connecting to it, so I have yet to flash the firmware on it for the first time. My goal is to be able to flash firmware/configure the switch on ethernet port 0, which will be driven by a microcontroller. I am still waiting on the software for the switch to be configured by the microcontroller, so I am trying to verify the switch by connecting to port 1, which has a standard ethernet phy.

I believe I have some simple things working and verified, but I am lacking the ability to connect to the host port via Ethernet. Here is what I have verified so far:

- I can strap the switch for SPI communication and see the pulses on the TIMER0 line every 1.25 seconds. This leads me to believe that my power/pinout/crystal oscillator is in a good enough shape to at least have the switch be able to communicate.

- When I strap the board for Ethernet communication, I have scoped the 125MHz clock signal (Px_TXC). It seems to be stable and clean.

I am trying to connect to it via the "...tsn_evaluation_util.exe" and I am not having any luck. Should I be able to connect to a switch that has never had any firmware flashed to it?

I know there is a driver example on github (this guy). I went to download it, and I am not able to build the project. It says that I am missing header information. I have provided a screenshot below:

Is there something I am missing for this project?

Any help you can provide would be greatly appreciated.

Thanks,

Missing files in the ADIN6310 driver software

vaughany24 — Mon, 23 Mar 2026 10:01:18 GMT

Hi,

I am trying to control the ADIN6310 device over SPI from a processor running embedded linux. I was following UG2287 which led me to download ADIN6310SWDR-Rel5.1.0 and try to build the ses-example-app and ses-tsn-configuration-app into my yocto environment with the SPIDEV switch set.

I initially attempted to follow the README but had to adjust bitbake recipes a little bit to make sure CMAKE was seeing all the source files… Unfortunately, I am still struggling to get it to build as it seem there are some header files (REG_registrar.h & SHL_command_line_interface.h) missing whichsome of the other source files refer to.

Has anyone had any success with this driver software or know where these missing header files come from?

Thanks

Steve

TXP to TXN pins' impedance when chip power is off

jsohnis — Thu, 26 Feb 2026 16:17:45 GMT

P4 & P5 are two ADIN110 media converter ports of our T1L 3 port switch.

They are typically used to pass T1L signal for concatenated links; downstream link connects to P4 upstream link connects to P5. P3 is a node port on the switch and not of interest here.

Object: In the event of power fail (VDD=0V) to the switch, we want to bypass the switch and connect P5 directly to P4. Basically, splicing P5 to P4 using a DPST relay for the wire pair.

We’ve implemented and preliminarily tested this using a DPDT relay.

Question:

Since P4 circuitry is still connected during power off for the splice to be enabled, the concern is that this may introduce a mismatching impedance to the spliced 110 ohm 2 wire cable.

We would like to know when ADIN1100 is powered off, is there a low impedance pathway between TXN & TXP pins, as the concern is that it would introduce 49.9+49.9 to the differential pair?
Or are there potentially other concerns, other than the obvious that could be introduced by the external DPDT relay?
Or turn on substrate diodes… limited by 49.9 ohm are activated
or...

Thanks..jonathan

Number of supported simultaneous Modbus TCP connections

BClendenin — Fri, 20 Feb 2026 20:06:25 GMT

How many simultaneous / concurrent Modbus TCP connections are supported on the ADIN2299?

No voltage on the DLDO1_1P1

AMike — Fri, 13 Feb 2026 05:41:09 GMT

Hello there,

has anyone encountered this problem? The same rail, 3.3V, is used to supply the ADIN2111 AVDD_H, AVDD_L, and VDDIO supply rails. Both DVDDx_1P1 1.1 V rails are being supplied from their internally DLDOx_1P1 1.1 V power supplies. There is an output voltage of 1.1 V on the DLDO2_1P1, but the DLDO1_1P1 output is 0 V. There are no shorts between DLDO1_1P1 and DVDD1_1P1 pins to the ground or any other pins or traces. Do you know what the problem might be? Your help is greatly appreciated.

Enable MDIO Clause 45 operations for ADIN6310

Kistler — Tue, 13 Jan 2026 14:57:54 GMT

Hi ADI,

We are trying to use an ADIN6310 (EVAL-ADIN6310) together with Marvell 88Q2221 Automotive Ethernet PHY that only supports Clause 45 commands for MDIO access.

From the documentation it only follows that using concatenated device and register address in SES_ReadPhyReg() ADIN6310 enables C45 register space access using four C22 operations, which we observe on the EVAL-ADIN6310.

Is it possible to enable Clause 45 commands to manage Marvell 88Q222X PHYs?

Best regards,

Vladimir

Cascaded ADIN6310 switches

chethan310 — Mon, 05 Jan 2026 11:28:22 GMT

Subject: Assistance with Cascaded ADIN6310 Switch Configuration

Message:

Hello,

We are working on configuring cascaded ADIN6310 switches with the following topology:

Processor (SPI) → Switch1 (Port2 SGMII) → Switch2 (Port3 SGMII) → Switch3 (Port2 SGMII)

For two switches, the configuration works as expected. However, when we attempt to configure the third switch using SES_AddDevice(), we encounter the following issues:

SES_AddDevice() returns an error (SES_AddDeviceError -1).
The third switch does not respond on the expected MAC or the default MAC.

We have followed the daisy-chain code snippet provided in the ADIN6310 software manual. For two switches, this approach works fine. The manual also mentions that “the application is responsible for adding static table entries.”

My questions are:

Is this daisy-chain configuration supported for three switches?
If yes, what is the correct procedure to configure the third switch?
- Should we add static forwarding entries manually for SES control packets?
The manual provides examples for a star configuration where Switch1 configures all other switches directly. How should we adapt this for a cascaded setup?

Please advise on the recommended approach or share any example code for adding static entries in a daisy-chain configuration.

Thank you for your support.

Using switch to extend number of network ports in host processor

harrisonNoja — Wed, 26 Nov 2025 23:45:58 GMT

We are currently using the ADIN6310 switch as a way to expand the number of network ports in our existing embedded Linux product as well as utilise some of the high level features to off load these from our main processor.

I am currently using Logical Mac groups as well as adding an entry into the static table for each of the mac groups to let all mac addresses pass through (passing 00:00:00:00:00:00 in MAC address mask) the specific network port and adding a tag on ingress.

These features seem to be targeting L2 traffic however for our use case we would like to use these features for L3 traffic also.

This is currently working for both L2 and L3 traffic and I have validated with basic network packets (Ethernet & IP) however have not yet done extensive testing. There is no documentation outlining this and I was just wondering if this is an expected use case for this switch and if there are any other features I could be utilising for this?

Thank you.

Base configuration for ADIN6310

BW866 — Wed, 19 Nov 2025 18:17:48 GMT

Hello,

I am nearing the process of getting a board made with the ADIN6310. I understand that it is a managed switch with a lot of configuration ability. I am curious though, if our purpose was to use it as a regular ethernet switch, would that require any interaction from the host? I ask because we plan on using the TSN features at some point in the future, but for our testing and software development, I would like to know what needs to be done in order for the device to function as a regular switch.

Thanks,

ADIN6310 Web GUI – Error When Selecting 802.1AS in Time Synchronization

ThejasKumar — Mon, 10 Nov 2025 10:23:36 GMT

When 802.1AS is selected in the ADIN6310 Time Synchronization section of the web GUI, an error occurs and the page fails to load. I have attached a screenshot for your reference.

ADIN3310 VDDIO_B

mxjnk — Tue, 04 Nov 2025 13:43:01 GMT

Hello,
I'm designing a product using the ADIN3310 together with ADIN1300 for two gigabit Base-T ports and one gigabit host port.
In the datasheet under the section Power consumption and thermal considerations it says " When operating at 1 Gbps on all six ports, use VDDIO_B at 1.8 V or 2.5 V. Operating at VDDIO_B = 3.3 V when all ports are at a 1 Gbps speed is not supported".
Does this "Operating at VDDIO_B = 3.3 V when all ports are at a 1 Gbps speed is not supported" also apply to the three port version of the chip or can i use 3.3V for VDIO_B when both VDDIO_B ports and the VDDIO_A port are running 1Gbps RGMII?

Best Regards

FRER Configuration, Setup, and Status - Seeking Monitoring Guidance

Dhevak — Tue, 14 Oct 2025 10:11:29 GMT

FRER Configuration, Setup, and Status - Seeking Monitoring Guidance

I'm implementing a Fault-Tolerant Redundancy (FRER, IEEE 802.1CB) configuration across two switches and two end devices (AM62p boards) to establish a redundant ring network.
I've observed the status counters on the Listener switch and now seek advice on the best way to monitor the replicated data transmission across the FRER ring using a host port,
specifically via Wireshark on Switch 1.

The core question is: How can I observe the data duplication (replication) that FRER creates, given that the Listener switch (Switch 2) removes the duplicate frames before they reach the end device (AM62p board 2)?

1. Network Configuration Overview

The setup consists of an FRER ring connecting two switches (Switch 1 and Switch 2), with the Talker (AM62p brd 1) connected to Switch 1 and the Listener (AM62p brd 2) connected to Switch 2.

1.1. Switch 1 (Talker Side)

Component Configuration Details
FRER Config Unicast/Multicast Miss Config: Port 1 and Port 2 set to 0.
Stream Table: For Ports 1, 2, 3. Identification Type: Source MAC / VLAN. VLAN: 100. Source MAC: 08-04-b4-31-12-42.
Talker Configuration: On Port 3 (connected to AM62p brd 1).
VLAN Config VLAN 100: Learn and forward for Ports 1, 2, 3.
MSTP Exception VLAN 100 added to the MSTP exception list.

1.2. Switch 2 (Listener Side)

Component Configuration Details
FRER Config Unicast/Multicast Miss Config: Port 0 and Port 1 set to 0.
Stream Table: For Ports 0, 1, 2. Identification Type: Source MAC / VLAN. VLAN: 100. Source MAC: 08-04-b4-31-12-42.
Listener Configuration: On Port 2 (connected to AM62p brd 2).
VLAN Config VLAN 100: Learn and forward for Ports 0, 1, 2.
MSTP Exception VLAN 100 added to the MSTP exception list.

1.3. End Devices

Device Configuration Details
AM62p brd 1 (Talker) VLAN ID 100 created and IP configured. Runs simple client to generate traffic. Source MAC: 08-04-b4-31-12-42.
AM62p brd 2 (Listener) VLAN ID 100 created and IP configured. Runs simple server to receive data via VLAN 100. Crucially, no duplicate data is received.

2. Observed FRER Status (Switch 2 - Listener)

The status counters on the Listener Switch (Switch 2) demonstrate the FRER functionality, specifically the sequence reconciliation logic.

2.1. Status with Both Ethernet Ports Connected (Redundant Path Active)

Counter Value Interpretation
Passed-pkts 114 Packets successfully forwarded to the Listener device.
Discarded-pkts 342 Significantly high count. These are the replicated frames discarded by the Sequence Reconciliation Function as they were duplicates of frames already received and passed. → This confirms the data duplication and reconciliation is working.
Out-of-order-pkts 0
Rogue-pkts 0
Lost-pkts 0

2.2. Status with One Cable Removed (Single Path Active)

Counter Value Interpretation
Passed-pkts 36 Packets successfully forwarded. (Fewer total packets due to reduced test duration/traffic).
Discarded-pkts 0 As expected. With only one path, no duplicate frames arrive, and thus no packets are discarded by the reconciliation function.
Out-of-order-pkts 0
Rogue-pkts 0
Lost-pkts 0

3. Monitoring Question and Proposed Approach

The status counters confirm that Switch 1 is replicating the traffic and Switch 2 is reconciling it. However, since the duplicate frames are removed at Switch 2, I cannot capture the duplicated data on the AM62p brd 2.

Critical Negative Observation During Monitoring Attempt:

When I configured a host port on Switch 1 for monitoring and set it as a standard "learn and forward" port while mirroring traffic from the ring ports:

The entire network bandwidth was severely reduced.

The switch started flooding (dumping) data out of many ports.

This behavior is consistent with MAC address flapping caused by the two identical,
replicated frames (Stream A and Stream B, both from MAC: 08−04−b4−31−12−42) hitting the switch's MAC address table via the two mirrored ports simultaneously.

Question:

What is the recommended method to monitor the duplicated traffic (the two distinct streams of identical, sequenced packets) that is traversing the FRER ring?

TSN IEEE 802.1AS , ADIN6310 gPTP Slave Fails to Detect/Sync to AM62 Master (BMCA Conflict)

Dhevak — Mon, 06 Oct 2025 12:40:22 GMT

ADIN6310(Master) with -AM62 (as slave) (Peer-to-Peer Mode)

ADIN 6310 as Master configuration

ref :image 1

Am62 configuration as Slave

command: ptp4l -i eth0 -H -2 -m -q -l 6 -f gptp_custom.cfg

gptp_custom.cfg
[global]
transportSpecific 1
domainNumber 0
clientOnly 1
logSyncInterval -3
logAnnounceInterval 0
priority1 255
delay_mechanism P2P

output status
Adin 6310 ref iamge 2.

AM62 output:
ptp4l[4534.688]: selected /dev/ptp0 as PTP clock
ptp4l[4534.742]: port 1 (eth0): INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l[4534.742]: port 0 (/var/run/ptp4l): INITIALIZING to LISTENING on INIT_COMPLET
ptp4l[4538.549]: port 1 (eth0): LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[4539.024]: port 1 (eth0): UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[4539.650]: rms 163212 max 324892 freq -38074 +/- 14495 delay 240 +/- 0
ptp4l[4540.650]: rms 3896 max 5970 freq -25301 +/- 5287 delay 241 +/- 0
ptp4l[4541.650]: rms 6489 max 6804 freq -13500 +/- 1711 delay 240 +/- 0
ptp4l[4542.649]: rms 4105 max 5459 freq -11222 +/- 166 delay 241 +/- 0
ptp4l[4543.649]: rms 1326 max 2193 freq -12485 +/- 481 delay 240 +/- 0
ptp4l[4544.649]: rms 237 max 369 freq -13884 +/- 302 delay 240 +/- 0
ptp4l[4545.649]: rms 390 max 406 freq -14558 +/- 104 delay 240 +/- 0
ptp4l[4546.649]: rms 257 max 333 freq -14715 +/- 11 delay 240 +/- 0
ptp4l[4547.649]: rms 86 max 144 freq -14640 +/- 34 delay 240 +/- 0
ptp4l[4548.649]: rms 24 max 33 freq -14529 +/- 23 delay 239 +/- 0
ptp4l[4549.649]: rms 28 max 33 freq -14490 +/- 6 delay 241 +/- 0
ptp4l[4550.649]: rms 12 max 18 freq -14493 +/- 5 delay 241 +/- 0
ptp4l[4551.649]: rms 6 max 11 freq -14495 +/- 5 delay 241 +/- 0
ptp4l[4552.649]: rms 6 max 11 freq -14490 +/- 5 delay 241 +/- 0
ptp4l[4553.649]: rms 9 max 12 freq -14478 +/- 6 delay 241 +/- 0
ptp4l[4554.649]: rms 5 max 7 freq -14487 +/- 7 delay 242 +/- 0
ptp4l[4555.649]: rms 7 max 15 freq -14488 +/- 9 delay 242 +/- 0

pcap LOG :
84 7.849925 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
85 7.850069 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
86 7.974904 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
87 7.975067 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
88 7.999743 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Announce Message
89 7.999857 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 78 Signalling Message
90 8.000015 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 72 Peer_Delay_Req Message
91 8.000133 08:04:b4:31:12:42 LLDP_Multicast PTPv2 68 Peer_Delay_Resp Message
92 8.000206 08:04:b4:31:12:42 LLDP_Multicast PTPv2 68 Peer_Delay_Resp_Follow_Up Message
93 8.099926 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
94 8.100109 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
95 8.224866 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
96 8.225059 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
97 8.331701 08:04:b4:31:12:42 LLDP_Multicast PTPv2 68 Peer_Delay_Req Message
98 8.331933 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 72 Peer_Delay_Resp Message

ADIN6310 with -AM62 (Peer-to-Peer Mode)

Component Role MAC Address Sync Interval
Grandmaster (GM) AM62 Host c0:d6:0a:f9:69:c9 1/8 s (125 ms)
Network Device ADIN6310 Switch 7a:c6:bb:11:11:13 Intended Slave/Boundary Clock

The ADIN6310 is configured in P2P (Peer-to-Peer) mode and intended to be a Slave to the AM62 Master.
Synchronization is failing because the ADIN is running as a competing Master or Grandmaster (GM).

The packet trace shows the ADIN (7a:c6:bb:11:11:13) is actively transmitting its own Sync and Follow_Up messages,
which should only be done by the elected GM. The AM62's Announce messages are being ignored, and the ADIN is not transitioning to the Slave state.

ADIN 6310 as Slave configuration

ref :image 3

Am62 configuration as Slave

command: ptp4l -2 -H -i eth0 -m -l 6 -f gptp_custom_master.cfg

gptp_custom_master.cfg

[global]
transportSpecific 1
domainNumber 0
priority1 10
logSyncInterval -3
logAnnounceInterval 0
delay_mechanism P2P

output status

AM62 output:
ptp4l[1356.082]: selected /dev/ptp0 as PTP clock
ptp4l[1356.116]: port 1 (eth0): INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l[1356.116]: port 0 (/var/run/ptp4l): INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l[1356.116]: port 0 (/var/run/ptp4lro): INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l[1357.919]: port 1 (eth0): new foreign master 7ac6bb.1111.110000-1
ptp4l[1359.529]: port 1 (eth0): LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES
ptp4l[1359.529]: selected local clock 0804b4.fffe.3112ea as best master
ptp4l[1359.529]: port 1 (eth0): assuming the grand master role

Adin 6310 ref iamge 4.

PCAP LOG

30.688251 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
30.688370 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
30.813268 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
30.813323 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
30.938289 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
30.938340 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
30.961916 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 78 Signalling Message
30.962056 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 72 Peer_Delay_Req Message
30.962141 c0:d6:0a:f9:69:c9 LLDP_Multicast PTPv2 68 Peer_Delay_Resp Message
30.962184 c0:d6:0a:f9:69:c9 LLDP_Multicast PTPv2 68 Peer_Delay_Resp_Follow_Up Message
30.962578 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Announce Message
31.000973 c0:d6:0a:f9:69:c9 LLDP_Multicast PTPv2 68 Peer_Delay_Req Message
31.001231 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 72 Peer_Delay_Resp Message
31.001330 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 72 Peer_Delay_Resp_Follow_Up Message
31.056993 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
31.057204 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
31.063326 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
31.063371 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
31.182004 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
31.182200 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
31.188345 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
31.188398 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
31.307013 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
31.307199 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
31.307376 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 78 Announce Message
31.313373 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
31.313428 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
31.432004 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
31.432197 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
31.438402 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
31.438457 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
31.556998 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
31.557195 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
31.563437 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
31.563500 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
31.682008 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
31.682194 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
31.688472 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
31.688519 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
31.806995 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
31.807192 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
31.813493 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
31.813547 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
31.931989 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
31.932189 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
31.938513 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
31.938562 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
31.961865 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Announce Message
31.961981 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 78 Signalling Message
31.962140 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 72 Peer_Delay_Req Message
31.962180 c0:d6:0a:f9:69:c9 LLDP_Multicast PTPv2 68 Peer_Delay_Resp Message
31.962216 c0:d6:0a:f9:69:c9 LLDP_Multicast PTPv2 68 Peer_Delay_Resp_Follow_Up Message
32.000978 c0:d6:0a:f9:69:c9 LLDP_Multicast PTPv2 68 Peer_Delay_Req Message
32.001196 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 72 Peer_Delay_Resp Message
32.001312 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 72 Peer_Delay_Resp_Follow_Up Message
32.056986 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
32.057186 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
32.063543 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
32.063592 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
32.181985 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
32.182185 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
32.188566 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
32.188615 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message
32.306990 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 64 Sync Message
32.307183 7a:c6:bb:11:11:13 LLDP_Multicast PTPv2 94 Follow_Up Message
32.307395 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 78 Announce Message
32.313594 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Sync Message
32.313644 c0:d6:0a:f9:69:c9 IeeeI&MS_00:00:00 PTPv2 58 Follow_Up Message

Time-Sensitive Networking (TSN) Configuration and Observation Issue in IEEE 802.1Qbv (TAS)

Dhevak — Mon, 06 Oct 2025 07:36:21 GMT

System Setup

Component Model/Platform Role
Endpoint (Sender) Texas Instruments AM62 (Linux) Traffic Source, responsible for VLAN/PCP Tagging.
TSN Switch Analog Devices ADIN6310 TAS Gatekeeper, responsible for Scheduling (802.1Qbv).
Synchronization IEEE 802.1AS (gPTP) Configured in Boundary Mode and assumed stable.

AM62 (Sender) Configuration (Traffic Classification)

The AM62 uses Linux Traffic Control (tc) to classify UDP traffic
DPort tc Filter Action Linux skb->priority
10001 action skbedit priority 0 0 (Highest)
10002 action skbedit priority 1 1 (Medium)
10003 action skbedit priority 2 2 (Lowest)

AM62 Traffic Generation Command

The output was observed while generating high-rate traffic, likely hitting DPort 10001 with a single plget instance:

./plget -i eth0 -m pkt-gen -p 3 -t ptpl2 -n 128 -a 70:ff:76:1d:8c:08 -l 1500
sleep 5
./plget -i eth0 -m pkt-gen -p 2 -t ptpl2 -n 128 -a 70:ff:76:1d:8c:08 -l 1500
sleep 5
./plget -i eth0 -m pkt-gen -p 1 -t ptpl2 -n 128 -a 70:ff:76:1d:8c:08 -l 1500

ADIN6310 (TSN Switch) Configuration

TAS Gate Control List (GCL)

The TAS GCL was configured with three entries for three intended priority queues :
GCL Entry Gate Duration (ns) Gate State (Assumed Queue Index)
Entry 0 125,000 Opens Queue for Prio 3 (e.g., Q3 - from "4th checkbox from right")
Entry 1 125,000 Opens Queue for Prio 2 (e.g., Q1 - from "2nd checkbox from right")
Entry 2 250,000 Opens Queue for Prio 1 (e.g., Q0 - from "1st checkbox from right")
GCL Cycle 500,000 ns (0.5 ms) Sum of Durations

Receiver End (AM62)

command
#Bash
while sleep 1; do ./plget -m rx-lat -f ipgap -n 128 -i vlan100 -t ptpl2 -f hwts; done

Observed Output (Single Transaction Phenomenon)

The output provided below shows the inter-packet gap (IPG) from the receiver, which was identified as traffic from a single observed queue ("queue 1 with prio mof 3").

The majority of IPGs are 12.224 ms, interspersed with much larger delays, including 263.943 ms and 266.559 ms some random large gaps.

Only one transaction is appeared in output

Clarification required : settings required for the ADIN6310 to correctly classify incoming PCP 0, 1, and 2 traffic into specific internal queues (e.g., Q3, Q1, Q0) for TAS scheduling.