I'd like to confirm some details regarding the latency of the ADIN6310/ADIN3310.
Q1: Is it acceptable to use the CUT-THROUGH value for SWITCH LATENCY regardless of whether HRS is used or not?
Q2: The datasheet doesn't mention RGMII; is it okay to treat SGMII PHY LATENCY as an approximation?
Q3: Please provide any other documentation regarding the device's latency.
Hello,
thanks for clarification.
1. The RGMII Bridge latency is the latency from RGMII port to another RGMII port. The total latency of the hop depends on the Tx/Rx latency of the external PHY used.
In the ADI evaluation boards, we use ADIN1300 PHY for Gb links, the latency of that PHY is documented in the datasheet. We do also take opportunity to reduce the RX latency of the PHY. During the init routine, the switch will check with the PHY what cable length it sees and the MSE mean squared error (signal quality on the diff pairs) and can make an assessment to reduce the RX latency and overall latency. See picture below for detail.
2. In the SGMII case, the switch has integrated SGMII/Serdes block, it connects directly to the RGMII interface. When considering the latency of the switch you need to consider both the RGMII latency and the SGMII numbers to understand what the switch contributes. If there is some external PHY (e.g. copper SFP module), the latency contributed from that would need to be added for overall latency.
Hello,
thanks for clarification.
1. The RGMII Bridge latency is the latency from RGMII port to another RGMII port. The total latency of the hop depends on the Tx/Rx latency of the external PHY used.
In the ADI evaluation boards, we use ADIN1300 PHY for Gb links, the latency of that PHY is documented in the datasheet. We do also take opportunity to reduce the RX latency of the PHY. During the init routine, the switch will check with the PHY what cable length it sees and the MSE mean squared error (signal quality on the diff pairs) and can make an assessment to reduce the RX latency and overall latency. See picture below for detail.
2. In the SGMII case, the switch has integrated SGMII/Serdes block, it connects directly to the RGMII interface. When considering the latency of the switch you need to consider both the RGMII latency and the SGMII numbers to understand what the switch contributes. If there is some external PHY (e.g. copper SFP module), the latency contributed from that would need to be added for overall latency.
