TXP to TXN pins' impedance when chip power is off

P4 & P5 are two ADIN110 media converter ports of our T1L 3 port switch.

They are typically used to pass T1L signal for concatenated links; downstream link connects to P4 upstream link connects to P5. P3 is a node port on the switch and not of interest here. 

Object: In the event of power fail (VDD=0V) to the switch, we want to bypass the switch and connect P5 directly to P4. Basically, splicing P5 to P4 using a DPST relay for the wire pair.

We’ve implemented and preliminarily tested this using a DPDT relay.

Question:

Since P4 circuitry is still connected during power off for the splice to be enabled, the concern is that this may introduce a mismatching impedance to the spliced 110 ohm 2 wire cable.

1. We would like to know when ADIN1100 is powered off, is there a low impedance pathway between TXN & TXP pins, as the concern is that it would introduce 49.9+49.9 to the differential pair?
2. Or are there potentially other concerns, other than the obvious that could be introduced by the external DPDT relay?
3. Or turn on substrate diodes… limited by 49.9 ohm are activated
4. or...

Thanks..jonathan