TXP to TXN pins' impedance when chip power is off

Hi Jonathan,

Would it be possible to have a block diagram of the complete system?

Regarding your questions, when the ADIN1110 is powered off, the MDI Circuitry (RXP/TXP/RXN/TXN pins) is in a high-impedance state. This should not impact the differential pair of 100 Ohms. However I reviewed the schematic and did find some issues:

Decoupling Capacitors:

The pin 24 (DVDD_1P1) has a decoupling capacitors of 0.68uF shared with DLDO_1P1, however it is required to use 0.1uF.

NC type pins:

As per the datasheet, we recommend the following pins (10, 11, 18 and 21) to be left open, but on the schematic both pin 18 and 21 have a coupling capacitors, could we make that change and make sure they are DNC.

MDI Circuitry:

We can observe a few diodes in the MDI circuitry, we do recommend to use low parasitic capacitance diodes as the MDI circuitry should have a maximum of 100pF of parasitic capacitance differentially.

Ground Pin:

On U5, the pin 6 (GND pin) seems to be set in DNI by the red cross, could we double-check and make sure it is properly connected to ground.

Kind Regards

Olivier

Below is a copy of my response that I sent to EZ in an email that was sent to me, as I thought was how the EZ sender intended the channel of response. as you can see by my embedded comments [js]-comments, I believe there are errors in EZ response based on datasheets. I've copied the relevant sections of datasheets as well. I look forward to confirmation or correction of my comments.

Thanks jonathan

Following is a copy of my embbeded response to email received from EngineerZone 

Hi Jonathan,

Would it be possible to have a block diagram of the complete system?

Regarding your questions, when the ADIN1110 is powered off, the MDI Circuitry (RXP/TXP/RXN/TXN pins) is in a high-impedance state. This should not impact the differential pair of 100 Ohms. However I reviewed the schematic and did find some issues:

[js]-great, that means we do not need to worry of loading or impedance mismatch. Hopefully no substrate dioses as well.

Decoupling Capacitors:

The pin 24 (DVDD_1P1) has a decoupling capacitors of 0.68uF shared with DLDO_1P1, however it is required to use 0.1uF.

[js]- based on datasheet and our application, 0.68u seems appropriate. Did I miss something? – see copy from DS below –

NC type pins:

As per the datasheet, we recommend the following pins (10, 11, 18 and 21) to be left open, but on the schematic both pin 18 and 21 have a coupling capacitors, could we make that change and make sure they are DNC.

[js]- based on datasheet and our application caps seems appropriate. Did I miss something? Ports are A-N, default to 2.4V (BMS, not automotive)  – see copy from DS below

MDI Circuitry:

We can observe a few diodes in the MDI circuitry, we do recommend to use low parasitic capacitance diodes as the MDI circuitry should have a maximum of 100pF of parasitic capacitance differentially.

[js]-these are all 1n4148 type <2pf

Ground Pin:

On U5, the pin 6 (GND pin) seems to be set in DNI by the red cross, could we double-check and make sure it is properly connected to ground.

[js]-pin 6 is connected to GND, same as EP, perhaps confused with proximal pin.

Kind Regards

Olivier

Hi Jonathan,

For the pin 24 (DVDD_1P1), the recommended value is 0.1uF as you pointed out on the datasheet but 0.68uF would be okay.

For the pins 18 and 21, it seems that you are not using the Rev.C datasheet of the ADIN1110, attaching below the correct connection for these pins. They are expected to be left open.

MDI Circuitry, the 1N4148 is 4pF which is low enough.

Kind Regards

Olivier

Hi Oliver,

Yes, we were early adopters of T1L and the ADI DS did not show p18 & p21 as NC, but rather as implemented by us.

we will make them NC. However, I do note that our testing with & without shows same performance.

I would appreciate if you could explain the reason for NC or the possible impact, harm or function of us connecting 1uf to p21 & 4.7uf to p18, as was originally recommended in  AN1100 DS Rev.Pre (pg 11 of 50).

thank you..jonathan 

Oliver,

I also note that in "1/2023—Rev. 0 to Rev. A" there is no mention of pin 18 & p21 updates!

I would suspect that the NC pins may be used during factory testing, and that 4.7uf & 1uf caps may charge during power on, but the concern on power off is they may dump their energy into the chip and turn on a substrate diode... comment?

Hi Jonathan,

Pin 18 and pin 21 are confirmed by design that they don't need to be connected and recommended to keep them NC, having the capacitors connected should not negatively impact the device, however removing these capacitors helps reducing the BOM of your design.

Kind Regards

Olivier

We're good, Thanks!