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ADIN2111 Problem with port 2

Category: Software
Product Number: ADIN2111

Hello,

I am currently working on the development of a smart sensor with SPE interface.
I am using the ADIN2111 to connect the smart sensors via daisy chain.
For the firmware, I used the demo package (ADIN2111 DeviceDriver -> LWIP Example) as a basis and adapted it to my hardware.
The firmware is configured so that all telegrams addressed to the device are forwarded to the host, and all other telegrams are forwarded to port 2 (and vice versa).
Now I have the problem that I cannot get a connection via the 2nd port. I have tried this with several smart sensors.

When debugging, I notice that in adi_phy.c ...

static adi_eth_Result_e phyInit(adi_phy_Device_t *hDevice)
{
//...

/* Read IRQ status bits to clear them before enabling IRQ. */
/* Hardware errors could be asserted if for, we don't care about the contents */
/* so we just discard the read values. */
result = PHY_Read(hDevice, ADDR_CRSM_IRQ_STATUS, &val16);
if (result != ADI_ETH_SUCCESS)
{
    goto end;
}
if (val16 & ADI_PHY_CRSM_HW_ERROR)
{
    result = ADI_ETH_HW_ERROR;
    goto end;
}

//...

}


... when configuring port 2, the return value of ADDR_CRSM_IRQ_STATUS (variable val) is 0x1080 or 0x0080, which indicates an internal fatal error.
The configuration of port 1 works without any problems.

Can anyone help me with this?

Best regards,
Matt

  • Hi Matthias,

    The ADDR_CRSM_IRQ_STATUS register value read indicates there might be an issue with the clock on Port 2. Are you supplying the correct clock source to P2_CLK_IN?

    Assuming the clock is physically connected correctly, have you modified anything other than the hardware layer in the example?

    Regards,

    Shazia

  • Hi Shazia,

    thanks for your feedback.

    We have connected P2_CLK_IN directly to CLK25_REF. To be on the safe side, I have measured again, the 25 MHz really arrive at P2_CLK_IN.

    Here is the corresponding circuit:


    In the firmware we have only adapted the files of the BoardSupportPackage (BSP) to our hardware, but I will check again whether something has been changed here by mistake.

    Best regards,
    Matt

  • Hi Matt,

    Yes, the clock input is indeed correct in the schematic.

    It is worth verifying if there's been any other changes in the FW that may have caused the issue. 

    Regards,

    Shazia