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KCC's Quizzes AQQ294 about a digital phase splitter design

		
	
				

			

									
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  •  Analog Employees  

			
			
			    	
			                    
                
				                on Nov 14, 2025 
				
			
			
		

		
		                     
				
        		

		    
		    		    
		    			

			    
1. Quote of the month: "I've learned that people will forget what you said, people will forget what you did, but people will never forget how you made them roll their eyes" - Robin Williams


2. New quiz of the month: AQQ294 about a digital phase splitter circuit


 


One has to build a digital 90 degrees phase splitter circuit giving an in-phase (LO_I) and a quadrature phase (LO_Q) square LO signals phased out 90° one to each other. Among the following 4 circuits, there is one which is not performing that role.


Question: can you localize it and tell why?


 


Good luck and try to be among the first ones!

			

			
									    

			        
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[edited by: ambugua at 4:00 PM (GMT -5) on 17 Nov 2025]
				

						
		                             
                        

    

                                            
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                on Dec 4, 2025 5:43 AM
            
            
						
			            		
    
		
								
	
    

		
		
    
		
    
                                
                                                            
    
					
    Circuit C.  If we assume LO_I is operating then LO_Q is always in phase so neither can change state.

    The analysis is relatively straight forward.  FFI configuration is common to A and B, and to C and D so the problem isn't with FF1.  FF2 in circuit B is identical to FF! with an inverted clock so that must also work.  Now assume LO_I is correct and run a truth table for FF2 on A, C and D.

    Circuits A and B won't actually give true quadrature because of the inverter delay.  CLK1 should be driven with a buffer with with a comparable propagation delay.

    Note also that clocked D flip-flops have an indeterminate power-on state.  They need to be reset (usually Q=0) prior to the first clock pulse to ensure correct operation from the first clock pulse. 
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Dec 4, 2025 5:43 AM
            
            
						
			            		
    
		
								
	
    

		
		
    
		
    
                                
                                                            
    
					
    Circuit C.  If we assume LO_I is operating then LO_Q is always in phase so neither can change state.

    The analysis is relatively straight forward.  FFI configuration is common to A and B, and to C and D so the problem isn't with FF1.  FF2 in circuit B is identical to FF! with an inverted clock so that must also work.  Now assume LO_I is correct and run a truth table for FF2 on A, C and D.

    Circuits A and B won't actually give true quadrature because of the inverter delay.  CLK1 should be driven with a buffer with with a comparable propagation delay.

    Note also that clocked D flip-flops have an indeterminate power-on state.  They need to be reset (usually Q=0) prior to the first clock pulse to ensure correct operation from the first clock pulse. 
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
				
						
				
				
		
		
    
			
		
    
	
    

    

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