KCC's Quizzes AQQ294 about a digital phase splitter design

Dear All,

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I think that the circuit C is the wrong one because the two output signals are in phase.

Circuit C fails to generate LO_I and LO_Q. Its output is dependent on the initial states of FF1 and FF2.  If Q1 and Q2 are 0/0 or 1/1, it will toggle back and forth between these two with each latching clock edge.  If Q1 and Q2 are 0/1 or 1/0, it stays in these states with each latching clock edge.

Circuit B.

Reason: it will produce either 0 degree phase shift (for (Q1, Q2) = (0,0) and (1,1)) or 180 degrees phase shift (for (Q1, Q2) = (0, 1) and (1, 0)). It will never produce a quadrature phase.

I think Circuit C is the odd one out because LO-Q will lag by 90 degrees rather than lead by 90 degrees.

C is not performing, the I and Q outputs are the same and in-phase.

Circuit C.  If we assume LO_I is operating then LO_Q is always in phase so neither can change state.

The analysis is relatively straight forward.  FFI configuration is common to A and B, and to C and D so the problem isn't with FF1.  FF2 in circuit B is identical to FF! with an inverted clock so that must also work.  Now assume LO_I is correct and run a truth table for FF2 on A, C and D.

Circuits A and B won't actually give true quadrature because of the inverter delay.  CLK1 should be driven with a buffer with with a comparable propagation delay.

Note also that clocked D flip-flops have an indeterminate power-on state.  They need to be reset (usually Q=0) prior to the first clock pulse to ensure correct operation from the first clock pulse. 

Bingo MikeLh , you get it, congrats!

Well done retiredEE , tht'as the correct answer!