KCC's Quizzes AQQ289 about a pipeline Analog-to-Digital Converter

Pipeline A/D Converter States

The status of bits B2, B1ubd B0 at the end of the 3rd active clock is 011

To fill in the voltages and bit values for a 3-stage pipelined ADC with ideal components, we need to understand the basic operation of each stage. Each stage typically consists of:

1. Sample and Hold (S/H)
2. Subtractor
3. Amplifier (usually gain of 2)
4. Comparator (1-bit ADC)
5. Multiplexer (MUX)

Given:

• Vref = 5 V
• Vin = 2 V
• Each stage resolves 1 bit, so B2 is MSB, B0 is LSB.
• Ideal components: no delay, no offset, no loss.

Stage 0 (First Clock Cycle)

• Vin = 2 V
• Comparator compares Vin to Vref/2 = 2.5 V
  • Since 2 V < 2.5 V → B2 = 0
• Subtractor: 2 V - 0 × 2.5 V = 2 V
• Amplifier: 2 V × 2 = 4 V
• This becomes input to next stage.

Stage 1 (Second Clock Cycle)

• Vin = 4 V
• Comparator compares 4 V to 2.5 V
  • 4 V > 2.5 V → B1 = 1
• Subtractor: 4 V - 1 × 2.5 V = 1.5 V
• Amplifier: 1.5 V × 2 = 3 V
• This becomes input to next stage.

Stage 2 (Third Clock Cycle)

• Vin = 3 V
• Comparator compares 3 V to 2.5 V
  • 3 V > 2.5 V → B0 = 1
• Subtractor: 3 V - 2.5 V = 0.5 V
• Amplifier: 0.5 V × 2 = 1 V (not used further)

Final Table

• Vx: Input to comparator
• Vy: Input to subtractor
• Vw: Output of amplifier

101

CLK    1    2      3

Vx2    2V  2V    2V

Vy2    2V  2V    2V

Vw2   4V  4V    4V

Vx1    0V  4V    4V

Vy1    0V  1.5V 1.5V

Vw1   0V  3V    3V

Vx0    0V  0V    3V

Vy0    0V  0V    0.5V

Vw0   0V  0V    1V

B2      0    0      0

B1      0    1      1

B0      0    0      1

The final conversion gives us an ADC output of 011, or a converted voltage of 1.875V.

2, 2, 4,0,0,0,0,0,0; 0, 0, 0
2, 2, 4, 4, 1.5, 3, 0, 0, 0; 0, 1, 0
2, 2, 4, 4, 1.5, 3, 3, 0.5, 1; 0, 1, 1

The pipeline ADC uses successive compare, subtract, and multiply by 2 to get a complete conversion. Usually, the conversion is done with a recirculating remainder to achieve the result. The main contributors of error are the x2 multiplication, and any offsets in the S/H.

Unfortunately, a poorly described problem, as the initial state of the 3 sample and hold blocks
is unspecified.

Commonly, for this type of ADC, the clock is running continuously, and as the input is specified
as 2 volts, the ADC reaches steady state after 3 clocks regardless of the initial state of the hold blocks.

Alternatively, if the 3 hold circuits are at 0V initially, then the result is