KCC's Quizzes AQQ272 about clock and data race

Thanks vanderghast for your prompt feedback! Mmmm I see a potential problem with circuit C. Let's consider the last stage (upper right): if there is no delay on the clock buffer (thus an ideal situation), the serial data out should get D0 previously present just before the active clock. But if the buffer delay, especially if it is longer than the DFF can occur after D0 has changed; thus missing the right data...

Thanks MTF_Walker  for your prompt input, like always! ! However, I am not sure to follow you with circuit C. Let's consider the last stage (upper right): if there is no delay on the clock buffer (thus an ideal situation), the serial data out should get D0 previously present just before the active clock. But if the buffer delay, especially if it is longer than the DFF can occur after D0 has changed; thus missing the right data..

Thanks rkg ! But not sure if Circuit C is the best... I agree the important thing is all the flip-flops should get their active clocks to get the data (actual Di going to Qi), but take the example of the last stage: the its buffer delay can be such that the output will take the NEW value D0

Thanks BrianE ! But I don't think I can agree with you... Circuit C, with their clock distribution, can let a Flip-Flop taking the already chnaged data from the previous stage..

Bingo AlexTru ! You get it, congratulations!

YEAH BernhardDwersteg , you get it, congratulations!

Thanks MarkThoren for your prompt reply! But the circuit A cannot be the best. In effect, with a such parralel clock distribution, it's difficult to predict which clock will act first. Let's take the case example the last (upper right) cell receives its clock much later than the previous stage: this latter will have already its data changed

B, because there will be delay from DFF to the last, so adding delay between each buffer will help with cascade. 

Circuit B, because it accounts for DFF delay. 

I'll admit I put too much focus on details for this quiz.  It's just a race issue on data hold time.
 
Circuit A: HT=FFdelay
Circuit B: HT=BUFdelay+FFdelay
Circuit C: HT=FFdelay-BUFdelay

Circuit B is the best since it has the longest hold time.  Circuit C is the worst since it is negative meaning data has been compromised.