KCC's Quizzes AQQ272 about clock and data race

I have more questions than an answer.
1) Are the D-flops gated or edge triggered?
2) Does the input data have to appear at the output in one clock period?
3) Is the serial input data synchronized with the clock?
4) How long does the input data remain valid relative to the clock?

I have more questions than an answer.
1) Are the D-flops gated or edge triggered?
2) Does the input data have to appear at the output in one clock period?
3) Is the serial input data synchronized with the clock?
4) How long does the input data remain valid relative to the clock?

I'll admit I put too much focus on details for this quiz.  It's just a race issue on data hold time.
 
Circuit A: HT=FFdelay
Circuit B: HT=BUFdelay+FFdelay
Circuit C: HT=FFdelay-BUFdelay

Circuit B is the best since it has the longest hold time.  Circuit C is the worst since it is negative meaning data has been compromised.

Thanks retiredEE  for the very valuable questions that can clarify better the questions!

1. yes, the DFF are edge triggered (at the positive edge)

2. Yes, the structure is a shift-register function: at every active clock, data are moved from the serial data-in to the serial data-out, bit per bit

3. Ideally, the clock edge occurs right at the middle of the data-in with enough setup and hold times. The race issue occurs when clock and data signals have different travel times.

4. As said in point 3: in ideal situation, the active clock edge occurs right in the middle of the data with enough setup and hold times.

Hope these precisions help!