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KCC's Quizzes AQQ272 about clock and data race

A new challenge (AQQ272 about a clock and data race)  is here:

The above 3 circuits use D-Flip-Flops (yellow) and clock buffers (blue). The buffers have slightly longer delays than the DFFs (it is due to both buffer intrinsic delay and long distances caused by the clock buffer tree).

Question: which of the 3 circuits is the best for data integrity? And why?

Good luck and try to be among the firs ones!

Please share your answer to view other submitted answers
  • Like that?  I am tempted to say Circuit A, the others add delays to clock intended synchronicity due to the cumulative delays of the OpAmps. And Circuit B is the worse. Circuit C can be very interesting, though, in cases where the delay of propagation of the OpAmp and of the delay of the response of the FlipFlop are roughly equal. In fact, in some cases, it can be prefered to Circuit A, but circuit, in general, Circuit A would be my first "try and see".

  • I just fall on the "buffers have slightly longer delays than de FlipFlop",  so I would change my answer to Circuit C, given the the clock signal would arrive AFTER the previous FliFlop did its output "computed" right before the interested FlipFop, interested to get the output of the previous one, would see to front edge of the clock signal.

  • Circuit A is the typical implementation of a SISO shift register, where each flop is clocked at the same time.  However, I think this works because the propagation delay through the clock gate is lower than the propagation through the flip-flop gates.  Circuit B clocks the LSB flop first, which wouldn't guarantee that the previous stages have valid data.  So, I think the answer must be C because this ensures that each stage has valid data on the previous flop's Q output before being transferred to the next flop's output.

  • Circuit C is best for data integrity.
    It is always better that the data signal appears before the clock signal so that there is no change of state of data when the clock is active.
    There  will be a delay from each flip flop. The buffers will provide adjustment to the delay and also prevent fall in  signal strength of the clock for longer distances.

  • Looks like Clock C is best because the clock drives only a single buffer, and the clock buffers accumulate in the same direction as data and therefore are guaranteed to lag it, so that S&H specs can be met (data present before clock edge)

  • Looks like Clock C is best because the clock drives only a single buffer, and the clock buffers accumulate in the same direction as data and therefore are guaranteed to lag it, so that S&H specs can be met (data present before clock edge)

  • Correct answer is: Circuits B, because it warrant the predefined sequence inside shift register, especially  accounting buffer delay.

     A: can work in the conditions when all buffers have exactly same delay (that is not realistic) , so it suffers from "glitches"  due to diference in buffer delays

    C: will always provide  on it's output D3 input - will work like delay line , but not shift register

  • I have more questions than an answer.
    1) Are the D-flops gated or edge triggered?
    2) Does the input data have to appear at the output in one clock period?
    3) Is the serial input data synchronized with the clock?
    4) How long does the input data remain valid relative to the clock?

  • Circuit A is the typical one for digital design. It relies on equal delays, so that the setup-hold time of the flipflops is compensated by the delay time of the flipflops. It does not allow for much variance in clock timing.

    Circuit B is much more safe, because the clock is delayed in reverse order of the shift process, so that safely each flip-flop sees the previous state of the preciding FFs Q output.

    Circuit C is prone to fail, because the buffer delay time eats up delay time within the flip-flop, and thus the preceding FFs output might just change while the next FF becomes clocked. This way, the output is not determined.

  • Alrighty, let's give this a shot:

    A is the best - it is the only one that has constant setup / hold times for each flip-flop. Assuming you meet setup / hold for the first flip-flop (data in from the outside world) and the second flip-flop (accounting for the first flip-flop's propagation delay), all other stages will meet timing.

    B and C will eventually fail if you keep adding more and more stages (or if the delay of the buffers are excessive):

    The clock to the first flip-flop in A will arrive "late", giving lots of hold time, but this will eventually encroach on setup time.

    The clock to the first flip-flop in B will arrive "early" or "on-time", with the clocks to later stages arriving later and later, giving more and more hold time... until setup time is violated.

    -Mark