KCC's Quizzes AQQ269 about a hysteretic control scheme on SMPS

The difference between VoL and VoH is 50 mV.

The off time slope is 10 mV/us so it will take 5 us to reach the set point, so off time is 5 us

The on time slope is 20 mV/us, so it will take 2.5 us to reach the set point, so on time is 2.5 us.

FET turn on and off times (tdly1 and tdly2) will be in the region of 10's of ns, a thousand time lower, so we can ignore for our estimate.

Period is off time + on time = 7.5 us, so approximate switching frequency is 133 kHz with a 33% duty cycle.

1/(7.5u + 2*tdly2 + 2*tdly1)

This one seemed too easy, hope I am not missing something.

The first slope is 10 mV/uS, so to traverse 50 mV takes 5 uS

The second slope is -20 mV/uS and takes 2.5 uS to traverse 50 mV

Total time between peaks of the angular waveform is therefore 7.5 uS, the sum of the absolute value of the two time periods

Taking the reciprocal calculates the frequency of 133.3 kHz

Here vpp=50, and Tpositive=(50/2) /10 and Tnegative=(50/2) /20.

So Tpositive=2.5 microsecond and Tnegative=1.25 microsecond. 

So total time period is 3.75 microsecond and so switching frequency will be (1/(3.75*10^-6) ) *10^3

1000/3.75=266.666khz approx 267

Freq is ~ 133kHz.  

I would say a little bit higher than 100 kH.

A single period would be 50/10 us  + 50/20 us  +2( tdy1 + tdy2 ). Without these two last timings, we arrive at 138kH. At "eye" scaled, the sum of the last two timings is about for on fourth of the total, so it reduces the frequency to a (round number)  100 kH.

Rise time= 5us, fall time=2,5us 

With tdly1 and tdly2 taken into account,  Freq= 1 / (7,5us + tdly1+tdly2) 

Ignoring the switching delays of the hysteretic comparator,
the output waveform period approximately equals:(50/10)us+(50/20)us=7.5us

Waveform frequency ~ (1/7.5us) = 133.33KHz

9 uSec period or 111 KHz

Bingo Martin, right answer; congratulations! The amazing thing to observe is the Bang-Bang converter principle is not to have a switching clock to perform the regulation; and despite of that the system, somehow, "auto-generates" a clock.