Post Go back to editing

1. Quote of the week: "I don't deserve this award, but I have arthritis and I don't deserve that either" - Jack Benny

Here above is a block diagram of a basic first order Sigma-Delta Analog to Digital Converter. OUT has the following the bit stream collected at the S-D modulator:

...1011011011101101 1011011011101101 1011011011101101…

The sequence in red is repeated continuously.

Question: with Vref=2.5 volt (and -Vref=-2.5 volt), what is the converted Vin value (in volt)?

• Hi KCC,

The 16-bit result 1011 0110 1110 1101 (or B6ED hex) is 46,829.

The ADC has 2^16 or 65,536 digital codes.

The full scale voltage is +2.5 - -2.5 = 5V

So the output voltage is 46,829 / 65,536 * 5V but referenced with respect to -2.5V

This is 3.572769V - 2.5V = +1.072769V.

• Thanks a lot Martin for your so prompt feedback! However, I have a small concern: thus you consider the bit sequence as a binary number with its MSB and LSB. In Sigma-Delta the bit sequence has an other nature... May be I am wrong, but let's wait on some more inputs from the audience...

• Ah, yes.  I wondered about that even as I send it.

The 1-bit stream will come out MSB first, so this will be at the right-hand side of the sequence instead of the left as we would usually read it.

In that case, the sequence (MSB first) is actually 1011 0111 0110 1101 = 0xB76D = 46,957 decimal.

The calculation is then 46,957 / 65536 * 5 -2.5 = 1.082535 V.

• More by deduction than otherwise, I will say the sequence is an unsigned integer from 0 to 65536. In fact, it gives 48221 (with the right handheld calculator, or probably with python), and so, the voltage would be (-2.5) + (48221/65536) x 5.0    (the 5.0 is the range in volt, while -2.5  is the measured voltage when the output is 0), that is 1.179 volt.

Note 1: Since the circuit does not seem to be "complex", I assumed that the number is not a signed integer.

Note 2: From the presence of the integrator, I assumed that the first bit to get out (the one to the extreme right) is the least significant and that there is no inversion of the octets as for some CPU.

• Hehe, not an easy one this quiz... In fact the bit stream coming out of the Sigma-Delta front end (as it is depicted in the diagram) is not a binary value; each bit has an equal intrinsic value. The confusion is probably due to the fact the given bit bit stream is taken at the output of the comparator, thus before the decimator. I will add that in the question. Meanwhile, may be you will rethink about the question?

• A precision to the quiz : the bit stream is collected at the output of the latched comparator, just before the filter& decimator block. Sorry if that has not been clearly mentioned.

• Thanks  for your prompt feedback! And your deduction is right; the bit stream is not a binary number, signed or unsigned... It has a different meaning. The question could be incomplete since I forgat to mention the bit stream is taken at the output of the comparator, just before the filter/decimator block. With that precision, may be you will reconsider your calculation?