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# KCC's quizzes AQQ260 about a technical article correction

1. Quote of the week: "No man goes before his time - unless the boss leaves early" - Groucho Marx

2. New quiz AQQ260 about a technical article correction

One (external) reader has noticed a mistake or imprecision in an ADI technical article:

The “faulty” section is displayed here below (note the BU is checking this for a coming quick update):

Questions:

1. What and where is the error or imprecision?
2. How would you correct it?

Good luck! And try to be among the firsts!

Kuo-Chang

P.S. Don't hesitate to share those weekly quizzes in EZ to colleagues or friends!

• OK, so, if I am considering an ADC with periodic sampling, then the reset (discharging) switch of the capacitor is missing in the circuit. And the frequency counter at the output of comparator. Do you mean this?

• You need to swap VIN and Vref in the circuit (and Vref needs to be negative for positive VIN). This way the "ramp" coming out from the integrator has always the same slope and you have direct proportionality between TINT and VIN

• And if you want an ADC, for all I know, you need to exchange Vin and (-)Vref, and add a switch in parallel to the capacitor (to discharge it), among other things. (And some more.)

• 1)  Error =>... proportional to the unknown voltage (TINT/VIN).

2)  ...The time it takes (TINT) for the integrator to trip the comparator is inversely proportional to the unknown voltage VIN and integrator gain (1/RC).  TINT=RC(Vref)/Vin.  In this...

Change Vin to 1/Vin in fig. 1b.

• Thanks  ! You have indeed localized the error in the article. And to be in accordance with the circuit diagram, the text should be modified in saying TINT is in fact inversely proportional to Vin. However, considering the whole article dedicated to ADC architectures, the "correction" has to be beyond: how to correct both the text and circuit in order to come with a right overal description of a correct single slope analog to digital converter. By keeping the circuit unchanged the target is not met obviously....

• A precision on the second question (I was probably somehow imprecise): the whole article is dedicated to ADC architectures, the "correction" has to be beyond the simple observation the text is wrong and need to be changed: how to correct both the text and circuit in order to come with a right overall description of a correct single slope analog to digital converter. By keeping the circuit unchanged the target is not met obviously....

• Bingo Gaetanao! That's the (mnimu) correction the BU has to do on that article! Congratulations!

• Yes! You get it  ! Congratulations! swapping Vin and Vref is the minimum and fundamental change to be done on the circuit in order to have it working as an ADC! Let's hope our BU will modify that article as soon as possible!

• Thanks  . I agree a counter block has to follow that integrator front end. But having the time delay inversely proporptional to Vin cannot give you the DAC function, regradless of the counter you put after it... A more fundamental change must be done on the integrator first...

• As mentioned in previous answers, Vin and Vref must be interchanged.