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KCC's Quizzes AQQ244 about Wafer Processing Yield puzzle

An IC fab is producing semiconductor chips. All the circuits are to be tested...
The process line has a final yield of 95%.

The automatic test equipment (ATE) put in place has the following characteristics:
1. When an IC is OK, the ATE test confirms it at a probability of 96%
2. When an IC is BAD, ATE test rejects it with a probability of 98%

Just before shipment to customer, one circuit is randomly selected.

Questions:
1. What is the probability the ATE tester has been wrong?
2. What is the probability that an IC (tested good) is in fact bad?

Try to be among the first ones giving the correct answers!

Good luck!

P.S. If you have colleagues around you and who can be interested in such quizzes, please pass the information!



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[編集者:StephenV、編集時刻: 19 Sep 2023 日 12:59 PM 時 (GMT -4)]
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  • I assume that ATE tester has only two states:  Good,  or Bad. (a third one, inconclusive, is not considered).

    Assume x is the probability that the IC is really good, so 1-x  is the probability that the IC is really bad  ( 0% = other that good or bad).

    1. When the IC is really good, ATE reports it good in 96% of the cases, (so bad, in 4%, since ATE has only two possible conclusions).

        Good and bad (in this case)  = x,  0.96 x = reported as good,   0.04 x = reported as bad (while good).

    2. When the IC is effectively bad,  ATE reports is as such 98%, so reports is as good in 2% of these cases:

        Bad IC, (1-x),  reported as such:  0.98 * (1-x)  while bad but reported good 0.02*(1-x)

    0. Assumed yield is the good reported good  +  the bad reported good  = 0.96x  + 0.02(1-x)  = 0.95   (I assume this how the "yield" is defined; another possible definition would be x = 0.95)

        which leads to  x = 93 / 94

    Q1: ATE is wrong by reporting bad while the IC is good  +  reporting good while the IC is bad : 0.04x + 0.2*(1.x)  =  3.9798%   (almost 4%)

    Q2: ATE reporting good a bad IC:  0.2(1-x)  = 0.0212%  ( or one IC each 4700)

  • An easier way to “visualize” the problem (without conditional probability, but by simple algebra):

    Define the 4 variables p, q, r and s:

     

    IC  is good

    IC  is bad

    Detected good

    p

    q

    Detected bad

    r

    s

     

    The 4 linear equations are:

    p + q + r + s  = 1     // (no other case, so total is at 100%)

    p = 0.96 ( p+r )  //  since p+r = total of IC is good, p = detected good at 96%

    s = 0.98 ( q+s )   //  since q+s  = total of IC is bad, s = detected as bad at 98%

    Missing one equation to solve the four unknowns. Given by the “yield” which, I don’t know, can be p+r  or p+q. One of these sums must be equals to 0.95.

    With p+r = 0.95, we obtain the system of equations:

    p

    q

    r

    s

    Second member

    1

    1

    1

    1

    1

    - 0.04

    0

    0.96

    0

    0

    0

    0.98

    0

    -0.02

    0

    1

    0

    1

    0

    0.95

     

    Gives: r=19/500, s=49/1000, q=1/1000, p= 114/125

    While if it is p+q  which is the yield

    p

    q

    r

    s

    Second member

    1

    1

    1

    1

    1

    - 0.04

    0

    0.96

    0

    0

    0

    0.98

    0

    -0.02

    0

    1

    1

    0

    0

    0.95

     

    Gives: r=93/2350, s=49/4700, q=1/4700 and p=116/1175

    (solutions from WolframAlpha, if there is an error, it is probably from my transcription)

    The answer of Q1 is  q+r  while the answer of Q2  is just q.

  • Actual yield (good chips) = 0.95
    Bad chips = 0.05
    Good chips that ATE confirms good = 0.96 * 0.95 = 0.912
    Good chips that ATE rejects = 0.04 * 0.95 = 0.038
    Bad chips that ATE rejects = 0.98 * 0.05 = 0.049
    Bad chips that ATE misses (tests good) = 0.02 * 0.05 = 0.001

    1) Probability that ATE tester is wrong = 0.038 + 0.001 = 0.039 [or 3.9%]
    2) Probability that an IC (tested good) is in fact bad = 0.001 [or 0.1%]

  • Big applause Martin! All answers are correct!

  • Thanks  , thus from your table, the probability that the ATE is wrong is 4% and that a BAD device is declared good is 0.1% ? I have well the 4% answer but not the second one. Can you recheck?

  • Indeed,  with the last equation corrected, it should be  (1 = 1%):  

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  • We can assume roughly 5% of defective chips (yield), as most defects are found.

    1. Of the 95% roughly good ICs, it directly finds 96%= 0.95*0.96=91.2%. Of the 5% defective is directly finds 98%. This makes up for 5%*98%=4.9%. Thus, is is wrong in 100%-4,9%-91.2%=3.9% of the results. 

    2. The OK test rate of 96% plays a minor role in IC test, because chips that are not OK, e.g. due to a contact failure, typically become re-tested. 

    With the ATE only recognizing 98% of defect ICs, this means, that 2% of the roughly 5% defective ICs are not discovered and therefore 0,02*0,05=0.1% of the ICs tested "good" still have an undiscovered fault. 

  • We can assume roughly 5% of defective chips (yield), as most defects are found.

    1. Of the 95% roughly good ICs, it directly finds 96%= 0.95*0.96=91.2%. Of the 5% defective is directly finds 98%. This makes up for 5%*98%=4.9%. Thus, is is wrong in 100%-4,9%-91.2%=3.9% of the results. 

    2. The OK test rate of 96% plays a minor role in IC test, because chips that are not OK, e.g. due to a contact failure, typically become re-tested. 

    With the ATE only recognizing 98% of defect ICs, this means, that 2% of the roughly 5% defective ICs are not discovered and therefore 0,02*0,05=0.1% of the ICs tested "good" still have an undiscovered fault. 

  • Thanks: since I have 0.1% for the first question, I tried to see where in your set of the 4 equations was established...

  • Bingo Bernhard! Correct answers, congratulations!