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# KCC's Quizzes: Buffers and Fan Out This is a typical problem for our VLSI designer colleagues: to distribute one same digital signal to a very large node (i.e. clock for registers, memories and counters). Propagation delays and skew must be minimized in order to avoid malfunctions.

The usual way is to build a chain of cascaded buffers having same fanout f (ratio between the output and input capacitors). With small N, delays of individual stage will be large and with higher number N, the total delay will be large: there is thus an optimum fanout f that minimizes the global propagation delay.

Questions:

1. What is the ideal fanout f (ratio between each output and input capacitances) that minimize the total propagation delay?
2. With CLOAD = 100 pF and CG=1pF, what should be an acceptable good number of stages?

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[edited by: emassa at 1:33 PM (GMT -5) on 26 Jan 2023]

## Top Replies

• It's not an easy one this time...

• 1. Two
2. Seven

Your answers are quite close to the "theoritical" (and thus ideal) values. Just wonder which equations you used?

• I assumed that the numbers must be integers.
- for the number of buffers it must be an integer (I don’t see how you could use half-a-buffer)
- for the “fanout” you could indeed use a non-integer number

In this case:
Number of buffers = 7
Fanout = seventh root of 100 = 1.93

• 1. 4

2. 5

• Hmm, with 7 stages and a fanout of 1.93 you get a total delay of 13.51T but I found a lower one:
With 5 stages and a fanout of 2.51 you get a total delay of 12.55T.
This seems to be the lowest delay possible.

• 1. f= N-th squared (f_tot), where f_tot is the total fan-out

2. f_tot=100, N_opt= optimal value of N, N_opt= ln(100)= 4.6

• Derivation of the equation Gaetano used is here: https://www.brown.edu/Departments/Engineering/Courses/engn1600/Lectures/EN160-08-complexGateSizeLayout.pdf wnich ties in with what Roland found by experimentation and iteration.

• I am just wondering how you design a chain of 4.6 buffers...

• Over-precisely... :-)