This is a typical problem for our VLSI designer colleagues: to distribute one same digital signal to a very large node (i.e. clock for registers, memories and counters). Propagation delays and skew must be minimized in order to avoid malfunctions.
The usual way is to build a chain of cascaded buffers having same fanout f (ratio between the output and input capacitors). With small N, delays of individual stage will be large and with higher number N, the total delay will be large: there is thus an optimum fanout f that minimizes the global propagation delay.
Questions:
- What is the ideal fanout f (ratio between each output and input capacitances) that minimize the total propagation delay?
- With CLOAD = 100 pF and CG=1pF, what should be an acceptable good number of stages?
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[edited by: emassa at 1:33 PM (GMT -5) on 26 Jan 2023]
