I am interested in using the PLL+VCO ADF4372 to generate a 15 GHz frequency signal.
The 100 MHz reference clock has the following phase noise values:
100 Hz -135 dBc/Hz 1000 Hz -153 dBc/Hz10000 Hz -159 dBc/Hz100000 Hz -161 dBc/Hz1000000 Hz -161 dBc/Hz10000000 Hz -161 dBc/Hz
The target Phase Noise at 15 GHz is:
-96 dBc/Hz @ 1 kHz;
-109 dBc/Hz > 10 kHz.
Is it possible to get these values with ADF4372?
Is there an optimal configuration that allows to obtain these values?
Thank you in advance.
You can use ADISIMPLL to check phase noise profile for interested output frequencies and adjust the loop filter configuration. You can model your reference with reference library editor and use the modeled reference. You can download the ADISIMPLL from the link below. Let me know if you see any issue.