PLL+VCO ADF4372: phase noise at 15 GHz RF out

Hi,

I am interested in using the PLL+VCO ADF4372 to generate a 15 GHz frequency signal.

The 100 MHz reference clock has the following phase noise values:

100 Hz                -135 dBc/Hz                             
1000 Hz              -153 dBc/Hz
10000 Hz            -159 dBc/Hz
100000 Hz          -161 dBc/Hz
1000000 Hz        -161 dBc/Hz
10000000 Hz      -161 dBc/Hz

The target Phase Noise at 15 GHz is:

-96 dBc/Hz @ 1 kHz;

-109 dBc/Hz > 10 kHz.

Is it possible to get these values with ADF4372?

Is there an optimal configuration that allows to obtain these values?

Thank you in advance.

Matteo