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FPGA Reference Designs

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Not Answered

ADRV9009-ZU11EG Multi-SOM usage: "Device or resource busy" 0

283 views

15 replies
on 18 Jan 2021
by mhennerich
Not Answered

Failed to add user layer 0

8 views

0 replies

on 18 Jan 2021 by Kunkunkun
Suggested Answer

Settings to be done in hdl 2018_r2 for 491MHz profile 0

179 views

7 replies
on 18 Jan 2021
by AdrianC
Not Answered

External Clock Multiplication on AD9467-FMC-250EBZ using AD9517 0

13 views

0 replies

on 18 Jan 2021 by Shant1406
Not Answered

ADRV9009-ZU11EG SOM bypass IOs from ADP5054 on carrier +1

45 views

2 replies
on 18 Jan 2021
by mhennerich
Not Answered

MGT REF CLOCK CONNECTION FOR DAC,ADC 0

120 views

4 replies

on 17 Jan 2021 by Sid@123
Not Answered

hdl_master Vivado mismatch error 0

81 views

2 replies

on 16 Jan 2021 by Kunkun
Not Answered

implementation of uart in cyclone iii ep3c120f780 and hardware peripheral SD details 0

11 views

0 replies

on 16 Jan 2021 by smadari408
Answered

ADRV9361-Z7035 reference design timeout errors with libiio example code 0

187 views

13 replies

on 15 Jan 2021 by da_dev33
Not Answered

AXI AD9361 Reset Signal 0

80 views

2 replies
on 15 Jan 2021
by imoldovan
Not Answered

Documentation regarding implemenation of DDS (Transport layer) in FPGA Reference design. 0

42 views

1 reply
on 15 Jan 2021
by andrei_g
Not Answered

JESD204rx and ADC in seperate clock domains 0

40 views

1 reply
on 13 Jan 2021
by AdrianC
Not Answered

l_clk with two AD9361s in Zynq 0

89 views

2 replies
on 13 Jan 2021
by srimoyi
Not Answered

fmcomms8 reduce Tx lanes from 8 to 4, tx status remains in CGS state 0

48 views

1 reply
on 12 Jan 2021
by mhennerich
Not Answered

Timing Constraints for AD40xx FPGA HDL 0

482 views

2 replies
on 12 Jan 2021
by andrei_g
Not Answered

how to configure ad-freqcvt1-ebz down converter using spi from zc706 board using the PL? 0

61 views

3 replies
on 12 Jan 2021
by andrei_g
Not Answered

Regarding LDO current rating in adrv9009-zu11eg evaluation board schematic 0

51 views

0 replies

on 11 Jan 2021 by Sid@123
Suggested Answer

I/O pins use in ADRV9361-Z7035/ADRV1CRR-BOB Board 0

339 views

10 replies
on 11 Jan 2021
by andrei_g
Not Answered

Altera HDL reference for 4x Adrv9009 (at least 2x Adrv9009) ? 0

282 views

6 replies
on 11 Jan 2021
by andrei_g
Not Answered

ADRV9009 SOM power sequencing with custom carrier +1

81 views

2 replies
on 11 Jan 2021
by mihai.bancisor@analog.com