I am currently trying implement an LFM Generator onto a Zedboard with the FMCOMMS3-EBZ with the Linux OS installed. However, I am not using the GUI and would like to do things from the terminal.
Currently, I am wondering where in the block design I should connect my LFM Generator. It has an output that provides the digital values of the signal I would like to transmit, as well as a valid signal. I would like to run the LFM Generator through the AD9361's DAC and transmit these values to a spectrum analyzer. I would also like to know if there is anything else I would have to enable once I have connected and programmed everything.
Thank you for your time. If you need me to clarify anything, please ask!
You want to put your IP between the upack and FIFO cores. Here is an example: Integrate FIR filters into the FMCOMMS2 HDL design [Analog Devices Wiki]
Moved to FPGA forum.
Thank you for your advice!
Looking at this example now, I have a few more questions:
1) In this example, the UPack has the port "dma_xfer_in" tied to VCC. However, in my block diagram, this port is nonexistent. Should I ignore this difference or is there a similar step I will need to complete?
2) Will the AD9361 still function properly if I leave the dac_data_* ports open on the UPack? The LFM Generator only takes in an enable signal and does not take in any other inputs to create its signal.
3) After properly connecting everything and programming to the board, how would I go about setting the "Transmit/DDS mode" to "DAC Buffer Output" without use of the GUI?
Again, thank you for your reply and for any and all help!
1. You can ignore it.
2. Yes you should be fine.
3. DDS control: AXI DAC HDL Linux Driver [Analog Devices Wiki]
You don't need the upack in this case.Is the LFM generator sending anything to the fifo?
You have to select the to set the DAC_DDS_SEL[3:0] to 0x2(Dac Buffer Output) to get the data from your outside of ad9361 core("DMA"). As a sanity test just select the DMA data trough the debug interface like in the Integrate FIR filters into the FMCOMMS2 HDL design [Analog Devices Wiki] example.Andrei