how to use SYNC pin to synchronize multiple adc

HI,

 I am using three dual channel adc ad9652. I want know how to use SYNC pin of those ADC to synchronize  ADC data output . Sampling clk for all adc is same and generated from a single crystal oscillator( same source). 

 May I need to generate sync pulse from FPGA and give to all adc SYNC pin simultaneously through multiple  FPGA pin   or need I just short the SYNC pin of all the ADC.

If need to generate a SYNC pulse from ADC then how  it is to be generate.?

Let me know how to use SYNC pin if multiple ADC are used . I never used multiple ADC and sync pin configuration.

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  • Hello,

    Synchronization happens at Clock rising edge where Sync signal is at high. Sync signal is a pulse type of signal. It is not necessarily to be half period of CLK+/-  or  specific value in period. Each sync signal at "high" should stay at " high" only at one rising edge of CLK. Again, sync signal is not to align the clock signal but it is to specify where(what rising edge of CLK) the clock divider works. In other words, the clock divider(not clock) can be synchronized by Sync input signal.

    No need sync signal if you don't use clock divider. For the synchronized clock distribution to multiple ADCs,

    clock distribution IC’s (like the HMC7043,ADCLK944) can be considered where one can delay clock edges between devices to compensate for different PCB delays to ensure higher sampling accuracy between devices.

    Thanks

    Tony

Reply
  • Hello,

    Synchronization happens at Clock rising edge where Sync signal is at high. Sync signal is a pulse type of signal. It is not necessarily to be half period of CLK+/-  or  specific value in period. Each sync signal at "high" should stay at " high" only at one rising edge of CLK. Again, sync signal is not to align the clock signal but it is to specify where(what rising edge of CLK) the clock divider works. In other words, the clock divider(not clock) can be synchronized by Sync input signal.

    No need sync signal if you don't use clock divider. For the synchronized clock distribution to multiple ADCs,

    clock distribution IC’s (like the HMC7043,ADCLK944) can be considered where one can delay clock edges between devices to compensate for different PCB delays to ensure higher sampling accuracy between devices.

    Thanks

    Tony

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