I am using three dual channel adc ad9652. I want know how to use SYNC pin of those ADC to synchronize ADC data output . Sampling clk for all adc is same and generated from a single crystal oscillator( same source).
May I need to generate sync pulse from FPGA and give to all adc SYNC pin simultaneously through multiple FPGA pin or need I just short the SYNC pin of all the ADC.
If need to generate a SYNC pulse from ADC then how it is to be generate.?
Let me know how to use SYNC pin if multiple ADC are used . I never used multiple ADC and sync pin configuration.
Thank you for your reply.
I am not using in chip clock divider option . The same clock signal is given to all ADC through buffer .
Now is there any need to use SYNC pin.?
In Datasheet of AD9652 they have given only timing requirement of setup(0.1ns) and hold time (0.1ns)but not maintained pulse duration of SYNC. Is it equal to ADC CLK period or HALF of ADC CLK period or any specific value ?
The propagation delay for SYNC may vary because on HW the SYNC pin is not common to all ADC. Through FPGA different FPGA pins were routed to different ADC SYNC pin , Though I can generate same SYNC signal and give to all ADC but propagation path delay vary.