Dear EngineerZone community
We are working with the ZC706+FMCDAQ2 for a telecom experiment. We are using the two output DAC channels to supply our optical modulators, and the two ADC to acquire data.. We would like to get an extra output digital signal from the FPGA to trigger our detection. How could we do this? Is it possible to output the clock signal from the FMC by one of the pins of the FPGA? or to get a clock signal directly from the FMC (enabling maybe the two extra DACS of the AD9114?). What would be the easiest option?
Also, the FMC-DAQ2 has a SMA input named Ext Trigger on top. I have not found information about this. Could this be used?
Thank you very much
the Ext Trigger is an input to the FPGA so you won't be able to use it as an output. There are no spare outputs on the DAQ2 card (AD9144 extra channels are connected to ground).
A simple solution to output a signal from the FPGA is to route it through one of the PMOD connectors, but the signal will be 3.3V and not very fast. Otherwise, you could use some kind of FMC breakout board and connect it to the other FMC from the ZC706 and route the signal through it.
Dear AdrianThank you for your help.
I need to output a 100 MHz signal (3.3V is fine) for triggering my detection,I will try what you say of routing the signal using a FMC breakout board. Therefore, what I have to do it to use the clock signal from DAQ2 (AD9523) to generate a 100 MHz signal and output it by the other FMC port, is this correct?
Another question; related to the Ext Trigger. Can it be use as a input to trigger my acquisition? This would be useful for my project. However, since I have not found information related to it, I wonder whether it is funcional.
If you intend to use the FMC breakout board, the voltage will probably be VADJ, not 3.3V necessarily.
For DAQ2, there is a RX clock and a TX clock coming from AD9523 to the FPGA which are used as a reference clock (one for CPLL and one for QPLL) for transceivers and also as device clock for the parallel data path. You could probably repurpose one of them, and use the other for both TX and RX reference, but this needs some changes in the HDL design and also in software.
Ext Trigger can theoretically be used to trigger data acquisition in HDL, but we haven't implemented this functionality. In our design, it's a simple signal connected to GPIO.
I tried to do what you suggested but I do not manage to achieve the result I need. Maybe I am doing something wrong. I am using the hdl_2017 with No-OS driver. In the system_top.v, I saw that there are two clock signals tx_ref_clk, and rx_ref_clk. I took the tx_ref_clk, divided and routed it out through one of the SMA i/o of the ZC706 (pin AD18, I also tried with a PMOD, same result). In the system wrapper I used the rx_ref_clk for both Tx and Rx. I get a signal out of the FPGA, however this signal is not synchorized to the sine wave that is provided by default from the DAQ2. What could be the problem?. Also you mentioned that I need to modify the software as well, what should I change in the sofware?
What do you mean by the sine wave that is provided by default from the DAQ2 ? The output of the two channels from AD9144 when generating data using DDS ? Can you give a more detailed description regarding the trigger signal characteristics ?