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Is the analog's hdl framework fine for my application?

Hi,

I am preparing for my master thesis, I have the following task and need your advice if it is possible to me to use the analog tools and hdl framework.

My task is to record data with an 1GSample, 200MHz bandwidth and 12 Bit ADC (1 Chanel ). For this I want to use the AD9234 ADC. I need to capture the waveforms for 20 uS after triggering, this gives me  240KBit of data. I need to do this 500 to 1000 times and have to average the waveforms, still need to store 1000 waveforms which gives me 240 Mbit data. After capturing the data I want to make some post processing using python, qt or Matlab.

My first Idea was to build this system using the analog hdl framework from GitHub. Analog provides most IPs as I understood. Also a JESD204b for communication, which is free to use when I make my software open right ? And normally I have to pay for the JESD204 IP ?

The design should be based on Industrial IO and should use a Xilinx Zynq-7000 FPGA. As I understood, the Analog designs using an DDR for the Processing Logic (PL) to capture the data from the ADC and use some magic to make this accessible to the processing system and linux, is this correct? How is this performed ?

I started by testing the task with an ADS7V2 and AD9680 evaluation boards, which works fine when recording the data. However, I want to build a own system for performing my task, is this possible to me to use the analog hdl repo or do I have to implement my own hdl description?

What would by a simple way to build a system, which is recording / capturing data with 1 GS and provides this data to Matlab which is running on the PS? Is this even possible?

I appreciate any hint or suggestions to my question.

best regards,

Nils

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  • Hi Adrian,

    ok I think I do understand now how ADI got data between PS and PL. When the data rate is to high, aid uses the fifo + DDR memory. 

    For testeiig purpose only I want to use the system without DDR so I can reduce my ads rate to 200 MS which gives me 0.2MS x 2 Byte = 400Bytes/S and when the AXI HP is capable of getting up to 2 Byte/S this should work without buffer correct?

    I attached my design as link as I have it right now, it is not working and I am still trying to understand everything. I removed my  DDR part from the tcl scripts and I added my board (krm3z30) to projects/common/... so I can build the project like ADI suggest it.

    The manufacture of the board only gives me a .vhd but all your systems us .v files so should I change the file of the manufacture to a .v file or should I implmenet a wrapper ?

    my design : ownCloud  

    Thanks  

    - Nils

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  • Hi Adrian,

    ok I think I do understand now how ADI got data between PS and PL. When the data rate is to high, aid uses the fifo + DDR memory. 

    For testeiig purpose only I want to use the system without DDR so I can reduce my ads rate to 200 MS which gives me 0.2MS x 2 Byte = 400Bytes/S and when the AXI HP is capable of getting up to 2 Byte/S this should work without buffer correct?

    I attached my design as link as I have it right now, it is not working and I am still trying to understand everything. I removed my  DDR part from the tcl scripts and I added my board (krm3z30) to projects/common/... so I can build the project like ADI suggest it.

    The manufacture of the board only gives me a .vhd but all your systems us .v files so should I change the file of the manufacture to a .v file or should I implmenet a wrapper ?

    my design : ownCloud  

    Thanks  

    - Nils

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