Products Mentioned

AD9680 Recommended for New Designs
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold...
Datasheet
AD9680 on Analog.com

Associated Drivers

AD9234 Recommended for New Designs
The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and...
Datasheet
AD9234 on Analog.com

Associated Drivers

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Is the analog's hdl framework fine for my application?



		

			

									
					    NilsMinor
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jun 12, 2018 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hi,
    
 
    I am preparing for my master thesis, I have the following task and need your advice if it is possible to me to use the analog tools and hdl framework.
    
 
    My task is to record data with an 1GSample, 200MHz bandwidth and 12 Bit ADC (1 Chanel ). For this I want to use the AD9234 ADC. I need to capture the waveforms for 20 uS after triggering, this gives me  240KBit of data. I need to do this 500 to 1000 times and have to average the waveforms, still need to store 1000 waveforms which gives me 240 Mbit data. After capturing the data I want to make some post processing using python, qt or Matlab.
    
 
    My first Idea was to build this system using the analog hdl framework from GitHub. Analog provides most IPs as I understood. Also a JESD204b for communication, which is free to use when I make my software open right ? And normally I have to pay for the JESD204 IP ?
    
 
    The design should be based on Industrial IO and should use a Xilinx Zynq-7000 FPGA. As I understood, the Analog designs using an DDR for the Processing Logic (PL) to capture the data from the ADC and use some magic to make this accessible to the processing system and linux, is this correct? How is this performed ?
    
 
    I started by testing the task with an ADS7V2 and AD9680 evaluation boards, which works fine when recording the data. However, I want to build a own system for performing my task, is this possible to me to use the analog hdl repo or do I have to implement my own hdl description?
    
 
    What would by a simple way to build a system, which is recording / capturing data with 1 GS and provides this data to Matlab which is running on the PS? Is this even possible?
    
 
    I appreciate any hint or suggestions to my question.
    
 
    best regards,
    
 
    Nils
    
									
			        
		
    

				
						
        

    
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                on Jun 21, 2018 2:50 PM
            
            
					
        
	
        

		
		
        
					
        Hi Adrian,
        
 
        thanks for the detailed informations 
        
 
        Ok I understand, so in VHDL AD9680 and AD9234 are pretty much the same  And I only need 1 GS 12 Bit 1 channel and about 200 MHz bandwidth so the AD9234 should work 
        
 
        The calculation of the throughoutput is very helpfull! I am using a ZXC7030 means F_AXI_MAX = 250 MHz. Is the Port the ACP AXI or normal AXI, both of them have 64 Bits width = 8 Byte? Or are they the same ports? The Datathrououtput is then 250 MHz x 8 Byte = 2 GByte/S between PL and Linux PS? But this means when using 1 GS ADC with 12 Bit (16 Bit) = 2 Byte , as you mentiond I have 2 GByte/S of Data between PL and PS. When I reduce this a bit (for testing only) I could run the system without DDR? And when using my DDR as FIFO there shouldn't be any problem. I can buffer the data in the fifo and pass it to the PS when it is ready.
        
 
        What do you mean with using the PL DDR instead of a fifo? For testsing purpose I would like use the system without DDR interface but in the final application I would like to use the 256 MB DDR of the PL for the fifo.
        
 
        Ok I understand 
        
 
        Many thanks for bringing light into the darkness.
        
 
        - Nils
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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													0
							
			
				
									
							        
			
			
			
          
            
						
                            
            
            				
            
                on Jun 21, 2018 2:50 PM
            
            
					
          
	
          

		
		
          
					
          Hi Adrian,
          
 
          thanks for the detailed informations 
          
 
          Ok I understand, so in VHDL AD9680 and AD9234 are pretty much the same  And I only need 1 GS 12 Bit 1 channel and about 200 MHz bandwidth so the AD9234 should work 
          
 
          The calculation of the throughoutput is very helpfull! I am using a ZXC7030 means F_AXI_MAX = 250 MHz. Is the Port the ACP AXI or normal AXI, both of them have 64 Bits width = 8 Byte? Or are they the same ports? The Datathrououtput is then 250 MHz x 8 Byte = 2 GByte/S between PL and Linux PS? But this means when using 1 GS ADC with 12 Bit (16 Bit) = 2 Byte , as you mentiond I have 2 GByte/S of Data between PL and PS. When I reduce this a bit (for testing only) I could run the system without DDR? And when using my DDR as FIFO there shouldn't be any problem. I can buffer the data in the fifo and pass it to the PS when it is ready.
          
 
          What do you mean with using the PL DDR instead of a fifo? For testsing purpose I would like use the system without DDR interface but in the final application I would like to use the 256 MB DDR of the PL for the fifo.
          
 
          Ok I understand 
          
 
          Many thanks for bringing light into the darkness.
          
 
          - Nils
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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