Is the analog's hdl framework fine for my application?

Hi,

I am preparing for my master thesis, I have the following task and need your advice if it is possible to me to use the analog tools and hdl framework.

My task is to record data with an 1GSample, 200MHz bandwidth and 12 Bit ADC (1 Chanel ). For this I want to use the AD9234 ADC. I need to capture the waveforms for 20 uS after triggering, this gives me  240KBit of data. I need to do this 500 to 1000 times and have to average the waveforms, still need to store 1000 waveforms which gives me 240 Mbit data. After capturing the data I want to make some post processing using python, qt or Matlab.

My first Idea was to build this system using the analog hdl framework from GitHub. Analog provides most IPs as I understood. Also a JESD204b for communication, which is free to use when I make my software open right ? And normally I have to pay for the JESD204 IP ?

The design should be based on Industrial IO and should use a Xilinx Zynq-7000 FPGA. As I understood, the Analog designs using an DDR for the Processing Logic (PL) to capture the data from the ADC and use some magic to make this accessible to the processing system and linux, is this correct? How is this performed ?

I started by testing the task with an ADS7V2 and AD9680 evaluation boards, which works fine when recording the data. However, I want to build a own system for performing my task, is this possible to me to use the analog hdl repo or do I have to implement my own hdl description?

What would by a simple way to build a system, which is recording / capturing data with 1 GS and provides this data to Matlab which is running on the PS? Is this even possible?

I appreciate any hint or suggestions to my question.

best regards,

Nils

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  • 0
    •  Analog Employees 
    on Jun 21, 2018 12:30 PM

    Hello Nils,

    The differences between AD9234 and AD9680 are highlighted at: Compare AD6674-LF 1000EBz vs  AD9680-LF1000EBZ / AD9234-LF 1000EBZ 

    Throughput needed by the ADC would be sampling rate x sample size (1gsps x 2bytes= 2GBps). ZC706 HP ports are 64 bits wide and have a maximum clock rate of  250MHz,according to ds191, which gives a maximum theoretical throughput of 250 x 8 = 2GBps (how fast data can be transferred to Linux) . If you go for the ZCU102 board, the HP port has 128 bits and maximum frequency of 333MHz, giving a maximum theoretical throughput of 5.328 GBps. 

    Moving the data from the FPGA to the PC is done through Ethernet, theoretical maximum of 1Gbps.

    The ZC706 is at the limit, not sure if it will work, probably you'll need to either use a large FIFO as a buffer or use the PL DDR instead of the FIFO.  Reducing the sampling rate should make it work without a FIFO. How much you need to reduce, I'm not sure, you need to test that.

    The adresses from Vivado should correspond to the addresses in the device tree.

    Regards,

    Adrian

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  • 0
    •  Analog Employees 
    on Jun 21, 2018 12:30 PM

    Hello Nils,

    The differences between AD9234 and AD9680 are highlighted at: Compare AD6674-LF 1000EBz vs  AD9680-LF1000EBZ / AD9234-LF 1000EBZ 

    Throughput needed by the ADC would be sampling rate x sample size (1gsps x 2bytes= 2GBps). ZC706 HP ports are 64 bits wide and have a maximum clock rate of  250MHz,according to ds191, which gives a maximum theoretical throughput of 250 x 8 = 2GBps (how fast data can be transferred to Linux) . If you go for the ZCU102 board, the HP port has 128 bits and maximum frequency of 333MHz, giving a maximum theoretical throughput of 5.328 GBps. 

    Moving the data from the FPGA to the PC is done through Ethernet, theoretical maximum of 1Gbps.

    The ZC706 is at the limit, not sure if it will work, probably you'll need to either use a large FIFO as a buffer or use the PL DDR instead of the FIFO.  Reducing the sampling rate should make it work without a FIFO. How much you need to reduce, I'm not sure, you need to test that.

    The adresses from Vivado should correspond to the addresses in the device tree.

    Regards,

    Adrian

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