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Is the analog's hdl framework fine for my application?


I am preparing for my master thesis, I have the following task and need your advice if it is possible to me to use the analog tools and hdl framework.

My task is to record data with an 1GSample, 200MHz bandwidth and 12 Bit ADC (1 Chanel ). For this I want to use the AD9234 ADC. I need to capture the waveforms for 20 uS after triggering, this gives me  240KBit of data. I need to do this 500 to 1000 times and have to average the waveforms, still need to store 1000 waveforms which gives me 240 Mbit data. After capturing the data I want to make some post processing using python, qt or Matlab.

My first Idea was to build this system using the analog hdl framework from GitHub. Analog provides most IPs as I understood. Also a JESD204b for communication, which is free to use when I make my software open right ? And normally I have to pay for the JESD204 IP ?

The design should be based on Industrial IO and should use a Xilinx Zynq-7000 FPGA. As I understood, the Analog designs using an DDR for the Processing Logic (PL) to capture the data from the ADC and use some magic to make this accessible to the processing system and linux, is this correct? How is this performed ?

I started by testing the task with an ADS7V2 and AD9680 evaluation boards, which works fine when recording the data. However, I want to build a own system for performing my task, is this possible to me to use the analog hdl repo or do I have to implement my own hdl description?

What would by a simple way to build a system, which is recording / capturing data with 1 GS and provides this data to Matlab which is running on the PS? Is this even possible?

I appreciate any hint or suggestions to my question.

best regards,


  • Hello,

    We don't provide explicit support for AD9234 in HDL, but you can probably use one of our other ADCs as a starting point for the port. We have support for the part in the Linux drivers.

    The ADI JESD204 IP is free to use if the project is open (as specified in GPL 2), yes. The Xilinx JESD204 IP is usually licensed and you need to pay for it, but you can check with them for a more accurate answer.

    Depending on the platform and the bandwidth requirement, we sometimes use PL DDR to capture data. You can check the DAQ2/ZC706 project to see how it's done. Basically, we capture the data from the ADC and stream it into PL DDR. After that, we use a DMA to transfer it to the PS DDR where is further processed or from where is transmitted to a PC through Ethernet.

    In our repository, we don't support ADS7V2 board, as it's used for evaluation and not prototyping. Do you have access to a ZC706/ZCU102 board ? We have better support for these. Depending on the system, you may not need to use PL DDR.

    My recommendation would be to use DAQ2 with ZC706. Matlab won't run on the PS, but you can transfer the data to the PC and process it there using Matlab. As it is, it uses PL DDR to capture ADC data, but if you only want to use a single channel, you may be able to capture the data directly to the PS memory.

    For FMCOMMS2 we provide an example on how to stream data directly to MATLAB, you can probably do something similar for you design:

    IIO System Object [Analog Devices Wiki] 



  • Hello Adrian,

    thanks for your response

    Yeah as I  understood I could use AD9680 it is mainly the same with higher accuracy ?

    Making my project open will be no problem since it is a thesis

    How is it possible to calculate the througoutput of the adc to the linux. Ok i understand the DDR is only a FIFO Buffer which stores the data which can not be passed via dma. But how fast is this? So an ADC with only 100MS would work without DDR by passing the data directly over dma to linux? So decreasing the DDR size from 1 GB to 256Mb in my case would only reduce the FIFO Size correct? When I decrease the Sample rate (for testing) could I remove the DDR interface of the PL?

    Yeah I understand that the system (PS+PL) only will grab data stores it and transfers it over ethernet. I could run matlab on a second host and write my own matlab drivers in order to control and stream the data from my device. I thnik I can reuse the FMCCOMMS2 matlabb code

    What about the addresses in the address table of vivado. How can I understand on how to adust them in order to work correctly in my application?

    Many thanks,


  • Hello Nils,

    The differences between AD9234 and AD9680 are highlighted at: Compare AD6674-LF 1000EBz vs  AD9680-LF1000EBZ / AD9234-LF 1000EBZ 

    Throughput needed by the ADC would be sampling rate x sample size (1gsps x 2bytes= 2GBps). ZC706 HP ports are 64 bits wide and have a maximum clock rate of  250MHz,according to ds191, which gives a maximum theoretical throughput of 250 x 8 = 2GBps (how fast data can be transferred to Linux) . If you go for the ZCU102 board, the HP port has 128 bits and maximum frequency of 333MHz, giving a maximum theoretical throughput of 5.328 GBps. 

    Moving the data from the FPGA to the PC is done through Ethernet, theoretical maximum of 1Gbps.

    The ZC706 is at the limit, not sure if it will work, probably you'll need to either use a large FIFO as a buffer or use the PL DDR instead of the FIFO.  Reducing the sampling rate should make it work without a FIFO. How much you need to reduce, I'm not sure, you need to test that.

    The adresses from Vivado should correspond to the addresses in the device tree.



  • Hi Adrian,

    thanks for the detailed informations

    Ok I understand, so in VHDL AD9680 and AD9234 are pretty much the same And I only need 1 GS 12 Bit 1 channel and about 200 MHz bandwidth so the AD9234 should work

    The calculation of the throughoutput is very helpfull! I am using a ZXC7030 means F_AXI_MAX = 250 MHz. Is the Port the ACP AXI or normal AXI, both of them have 64 Bits width = 8 Byte? Or are they the same ports? The Datathrououtput is then 250 MHz x 8 Byte = 2 GByte/S between PL and Linux PS? But this means when using 1 GS ADC with 12 Bit (16 Bit) = 2 Byte , as you mentiond I have 2 GByte/S of Data between PL and PS. When I reduce this a bit (for testing only) I could run the system without DDR? And when using my DDR as FIFO there shouldn't be any problem. I can buffer the data in the fifo and pass it to the PS when it is ready.

    What do you mean with using the PL DDR instead of a fifo? For testsing purpose I would like use the system without DDR interface but in the final application I would like to use the 256 MB DDR of the PL for the fifo.

    Ok I understand

    Many thanks for bringing light into the darkness.

    - Nils

  • In our reference designs, we don't use the ACP port, so I don't know details about it. We use the HP ports of the PS7.

    The PL DDR FIFO is actually a store and forward memory. You could use a FIFO which at the same time reads data from the ADC and write data to the DMA, and if the FIFO is large enough and the HP port is fast enough, the FIFO doesn't overflow while transfering your data. We don't provide this type of FIFO. The terminology we use is a bit unfortunate.



  • Hi Adrian,

    ok I think I do understand now how ADI got data between PS and PL. When the data rate is to high, aid uses the fifo + DDR memory. 

    For testeiig purpose only I want to use the system without DDR so I can reduce my ads rate to 200 MS which gives me 0.2MS x 2 Byte = 400Bytes/S and when the AXI HP is capable of getting up to 2 Byte/S this should work without buffer correct?

    I attached my design as link as I have it right now, it is not working and I am still trying to understand everything. I removed my  DDR part from the tcl scripts and I added my board (krm3z30) to projects/common/... so I can build the project like ADI suggest it.

    The manufacture of the board only gives me a .vhd but all your systems us .v files so should I change the file of the manufacture to a .v file or should I implmenet a wrapper ?

    my design : ownCloud  


    - Nils

  • Hello Nils,

    Theoretically it should work without an additional buffer. We have designs working at that rate without using intermediary buffers. I'm not familiar with the resources of krm3z30, but if it has an fpga equivalent with the zedboard or better, it should work.

    I think Vivado supports mixed languages, so it should work with VHDL also. Depending on complexity, you can probably change their system_top to a verilog version without an additional wrapper, but it's up to you. I don't have too much experience with VHDL, so I cannot give you specific pointers. Taking as an example one of our system_top.v should be a good start.



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