VerilogHDL language writing AD5761R driver, is there a reference case?

The program I wrote is not correct, no analog voltage.

  • Could you please look at the code for me?I can't find fault.   thank you!

    module ad5761(en,clk,din,sync,sclk,dout,ldac,RESET);

    input en;

    input clk;

    output wire RESET ;

    input din;

    output sync;

    output sclk;

    output dout;

    output ldac;

    reg temp;

    reg sync_r= 1'b0;

    reg sclk_r= 1'b0;

    reg dout_r;

    reg ldac_r= 1'b1;

    reg  cnt=8'd0;

    reg  i=8'd0 ;

    always@(posedge clk )

    if(en)

         case(i)

              0:

                begin

                   temp<=din;

                     i<=i+1'b1;

                     ldac_r<=1'b1;

                end

           1:

               begin

                   if(cnt==0)sync_r<=1'b1;

                   if(cnt==3)

                   begin

                        cnt<=0;

                        i<=i+1;

                        sync_r<=1'b0;

                   end

               else

                        cnt<=cnt+1'b1;

           end

         2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25:

           begin

                   if(cnt==0)

                   begin

                      dout_r<=temp[25-i];

                        sclk_r<=1'b1;

                   end

               if(cnt==1)

                   begin

                       i<=i+1'b1;

                        cnt<=0;

                        sclk_r<=1'b0;

                   end

              else

                    cnt<=cnt+1'b1;

         end

          26:begin

              if(cnt==0)

                    sync_r<=1'b1;

              if(cnt==9)

                 begin

                       cnt<=0;

                         i<=i+1;

                 end

              else

                  cnt<=cnt+1'b1;

              end

         27:

            begin

                 ldac_r<=1'b0;

                   i<=i+1'b1;

              end

         28:

         begin

              ldac_r<=1'b1;

                i<=0;

       end

         endcase

          

    assign sync=sync_r;

    assign sclk=sclk_r;

    assign dout=dout_r;

    assign ldac=ldac_r;

    assign RESET = 1 ;

    endmodule

  • 0
    •  Analog Employees 
    on Apr 25, 2018 4:21 AM

    We do not have a reference design, but this device has a simple interface. Make sure that the SYNC is connected to the chip select (CS) line of the SPI controller in FPGA. You should also control the RESET and LDAC pins with a GPIO controller. The RESET should be in high state and you should assert LDAC after each SPI transaction for at least one clock cycle.

  • 0
    •  Analog Employees 
    on Apr 25, 2018 5:03 AM

    Sorry, but we're not providing this kind of support. 

    But I can give you a few suggestions. Try to make a test bench for your design, and make sure that your design is working in simulation. Then when debugging in hardware you can use an embedded logic analyzer (ILA or SignalTap) to monitor the internal signals of your design. 

    Good luck!

  • Do you need to do register configuration when testing? My register input order,value:

    software_reset_registe_cmd = 24'b0000_1111_0000_0000_0000_0000 ;

    Control_register_cmd = 24'b0000_0100_0000_b0010_0010_1000;

    input data={8'b00000000,din};

  • The serial interface timing is ready, but what order should the register be written from SDI?My analog voltage won't come out.